Thanks Richard.
Committed with V2:
https://gcc.gnu.org/pipermail/gcc-patches/2023-December/640172.html
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2023-12-11 20:12
To: juzhe.zhong\@rivai.ai
CC: Robin Dapp; gcc-patches
Subject: Re: [PATCH] RTL-SSA: Fix ICE on record_use of RTL_SSA for
Thanks Richard.
It would be great if you are ok I can fix it in RTL_SSA.
I leverage your LRA patch in RTL_SSA:
else
{
// Record the mode of the largest use. The choice is arbitrary if
// the instruction (unusually) references the same register in two
// different but equa
Oh. I just confirmed. V1SI make perfect sens since we never apply partial
vectorization for VLSmode.
Drop this patch and going to refactor reduction pattern to fix this issue.
Thanks.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-12-11 17:11
To: juzhe.zh...@rivai.ai; gcc-patches
CC: rdapp
I think it's reasonable refactor reduction instruction pattern work around this
issue.
Going to send a patch to apply this solution.
So drop this patch. Sorry for bothering Richard S.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-12-11 17:01
To: Juzhe-Zhong; gcc-patches
CC: rdapp.gcc; r
>> I'm not sure we'd want to model it as subreg here (endianness etc?).
>> Could we have a VLS-mode equivalent for the VLA mode that only holds
>> one element?
Yes. This is the last chance to walk around it here but we will end up with
more patterns.
since reduction dest operand always LMUL = 1 m
