> It is nicely generic as well, but requires more insns than this if your
> ISA does not have a full complement of logical ops. Well, just an
> "andnot" is enough, you don't actually need eqv here.
Indeed, and it's rather spectacular for 64-bit operations on 32-bit machines
because the sign bit
> And the generic one for div is as good as it gets as well I suppose?
There is no support for div at all, only add/sub/neg/mul.
--
Eric Botcazou
On Mon, Oct 24, 2016 at 11:03:25PM +0200, Eric Botcazou wrote:
> > Let's see. Completely untested. Inputs in regs 3 and 4, output in reg 3.
> > 32-bit code all the way.
> >
> > add:
> > eqv 9,3,4
> > add 3,3,4
> > xor 4,3,4
> > and. 4,9,4
> > blt
> >
> > sub:
> > xor 9,
> It's better than the generic branch sequence below, or yours. It still
> sucks, obviously.
OK, I thought you were talking about the double-width result. The non-branch
sequence I posted is the generic non-branch sequence (that Ada was using).
> Let's see. Completely untested. Inputs in reg
On Mon, Oct 24, 2016 at 06:14:48PM +0200, Eric Botcazou wrote:
> > Maybe the best you can do is generate the double-width result, and then
> > check if the upper halve is the sign extension of the lower halve. Maybe
> > some trickery can help (for add/sub/neg at least).
>
> That's inefficient, ev
> Maybe the best you can do is generate the double-width result, and then
> check if the upper halve is the sign extension of the lower halve. Maybe
> some trickery can help (for add/sub/neg at least).
That's inefficient, even for additive operations.
> You can also just FAIL the expander if !TA
On Mon, Oct 24, 2016 at 01:20:09PM +0200, Eric Botcazou wrote:
> > You can use SO instead, but then you have to make sure it is clear before
> > you run the OE=1 instruction. SO of course is the cheapest way to access
> > overflow (it is copied to the CR field on any compare or recording insn).
>
> But not in the "Base" category. GCC should not generate mcrxr unless some
> flag enabling the "Embedded" category is set (this can of course be set
> via -mcpu=), or we have ISA 1.xx . It is probably nicer if we treat
> mcrxr separately, with an -mmcrxr flag, with TARGET_MCRXR.
OK, that makes
On Mon, Oct 24, 2016 at 11:54:27AM +0200, Eric Botcazou wrote:
> > mcrxr does not exist anymore. It is not implemented in any IBM non-embedded
> > CPU since POWER4. PA6T does not have it either. In some versions of the
> > 2.0x ISA it does exist, but only in the optional "embedded" category.
>
> mcrxr does not exist anymore. It is not implemented in any IBM non-embedded
> CPU since POWER4. PA6T does not have it either. In some versions of the
> 2.0x ISA it does exist, but only in the optional "embedded" category.
Yes, it exists in all (public) versions of the unified 2.0x ISA.
> Lin
Hi Eric,
Thanks for the patch. Unfortunately there is a big problem with it :-(
On Sat, Oct 22, 2016 at 01:03:33AM +0200, Eric Botcazou wrote:
> this implements support for signed overflow arithmetic on PowerPC. It's an
> implementation for Power ISA v2.0x, i.e. it doesn't take account the new
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