Hi Eric,
Thanks for the patch. Unfortunately there is a big problem with it :-(
On Sat, Oct 22, 2016 at 01:03:33AM +0200, Eric Botcazou wrote:
> this implements support for signed overflow arithmetic on PowerPC. It's an
> implementation for Power ISA v2.0x, i.e. it doesn't take account the new OV32
> flag introduced in v3.0. It doesn't implement unsigned overflow arithmetic
> because my understanding is that the generic support already generates
> optimal
> code in most cases on PowerPC for unsigned.
>
> It introduces a new MODE_CC mode (CCVmode) which represents the OV flag of
> the
> XER, and the overflow arithmetic instructions are paired with a mcrxr.
mcrxr does not exist anymore. It is not implemented in any IBM non-embedded
CPU since POWER4. PA6T does not have it either. In some versions of the
2.0x ISA it does exist, but only in the optional "embedded" category.
Linux emulates mcrxr, but that is very slow. You could use mfxer, but
that is a slow instruction as well (it is microcoded).
> The
> comparisons are written in terms of UNSPECs because I used that for Visium
> and
> SPARC, but I can rewrite them a la x86/ARM if requested.
That may work better. It also may be better if you expose the OV bit
as a separate reg (just like we have CA), instead of putting two machine
insns in each template.
> @@ -21863,6 +21865,14 @@ print_operand (FILE *file, rtx x, int co
> /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
> output_operand. */
>
> + case 'C':
> + /* X is a CR register. Print the index number of the CR. */
> + if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
> + output_operand_lossage ("invalid %%E value");
"%%C value", no space after "!".
> + else
> + fputs (reg_names[REGNO (x)], file);
> + return;
Why is this needed, do you have an assembler that wants register names
but not for mcrxr?
Segher
