RE: [EXTERNAL]RE: [PATCH ]RISCV :Added MIPS P8700 Subtarget

2025-05-12 Thread Umesh Kalappa
}; > > +/* Costs to use when optimizing for MIPS P8700 */ static const struct > +riscv_tune_param mips_p8700_tune_info = { > + {COSTS_N_INSNS (4), COSTS_N_INSNS (4)},/* fp_add */ > + {COSTS_N_INSNS (5), COSTS_N_INSNS (5)},/* fp_mul */ > + {COSTS_N_INSNS (17), COSTS_N

RE: [EXTERNAL]Re: [PATCH]RISCV :Added MIPS P8700 Subtarget

2025-04-29 Thread Umesh Kalappa
/ + true, /* use_divmod_expansion */ + false, /* overlap_op_by_pieces */ + RISCV_FUSE_NOTHING, /* fusible_ops */ + NULL, /* vector cost */ + NULL, /* function_align */ + NULL, /* jump_align */ + NULL, /* loop_align */

RE: [EXTERNAL]Re: [PATCH]RISCV :Added MIPS P8700 Subtarget

2025-04-21 Thread Umesh Kalappa
Thank you @Jeff Law for the suggestions and >> Just quickly scanning the insn reservations, I suspect you're missing many >> cases and the compiler will trip assertion failures if you are missing cases. Sure will look at it . >> You might want to look at these values more closely. If you have

RE: [EXTERNAL]Re: [PATCH] RISCV :Added MIPS P8700 Subtarget.

2025-04-11 Thread Umesh Kalappa
Thank you @Kito Cheng for early suggestions ,we will break down the patch like suggested and address the below comments . ~U -Original Message- From: Kito Cheng Sent: 11 April 2025 12:37 To: Umesh Kalappa Cc: gcc-patches@gcc.gnu.org; kito.ch...@sifive.com; Jesse Huang ; pal...@dabbel