Hi Lin,
On Thu, 17 Apr 2014 22:29:14, Lin Zuojian wrote:
>
> Hi Bernd,
> I have my copyright mark signed and the process has completed. Now I
> am going to answer two more questions before my patch can be
> commited right?
>
> Did you copy any
> files or text written by someone else in these chang
Hi Bernd,
I have my copyright mark signed and the process has completed. Now I
am going to answer two more questions before my patch can be
commited right?
Did you copy any
files or text written by someone else in these changes?”
no
[Which files have you changed so fa
Hi,
GCC changes(http://gcc.gnu.org/gcc-4.9/changes.html) says:
"AddressSanitizer, a fast memory error detector, is now available on
ARM."
But I test it,and find PR60281 is still there!That means the wrong
shadow bytes will still populate using stm instructions.
So,I don't
Hi Bernd,
Post stations are not that 90's,and they charge.It took me $30 to
post the file to USA.It's so inconvenient and expensive that I can't
send a scaned version.
--
Regards
lin zuojian
On Wed, Apr 09, 2014 at 06:47:56PM +0800, lin zuojian wrote:
> Hi Bernd,
> I am asking th
Hi Bernd,
I am asking them if they would accept a scaned image version.Post
station is so 90's
--
Regards
lin zuojian
Hi Lin,
> Seem we are not talking the same problem.You should first make sure
> what has been going wrong first.
Maybe I misunderstood your point.
> And I will sign it.
> --
> Regards
> lin zuojian
Ok, then please do it.
Once you have signed it, and got the approval by a global GCC reviewer,
Hi Bernd,
Seem we are not talking the same problem.You should first make sure
what has been going wrong first.
And I will sign it.
--
Regards
lin zuojian
Hi Lin,
thanks for clarifying this.
If you say you can't sign the FSF copyright assignment,
we can't use your patch, I'm afraid.
Well, I was curious how to proceed, because these unaligned
stm instructions are also a problem under linux.
The test cases don't fail, because the exception handler
Hi Bernd,
in a way,yes.I am testing it.Since I don't have a FSF copyright
mark,and I have no idea what is that file saying,I can't commit my
patch.If you are interested in it,please help me commit it.
By the way,there is another way to work it out,and it has been
mentioned in t
Lin,
are you still working on this?
Thanks
Bernd.
Thanks Jakub
--
Regards
lin zuojian
On Tue, Mar 04, 2014 at 10:15:31AM +0100, Jakub Jelinek wrote:
> On Tue, Mar 04, 2014 at 04:44:57PM +0800, lin zuojian wrote:
> > On Tue, Mar 04, 2014 at 09:04:56AM +0100, Jakub Jelinek wrote:
> > > On Tue, Mar 04, 2014 at 11:11:45AM +0800, lin zuojian wrote:
>
On Tue, Mar 04, 2014 at 04:44:57PM +0800, lin zuojian wrote:
> On Tue, Mar 04, 2014 at 09:04:56AM +0100, Jakub Jelinek wrote:
> > On Tue, Mar 04, 2014 at 11:11:45AM +0800, lin zuojian wrote:
> > > Without aligning the asan stack base,this base will only 64-bit aligned
> > > in ARM machines.
> > >
On Tue, Mar 04, 2014 at 09:04:56AM +0100, Jakub Jelinek wrote:
> On Tue, Mar 04, 2014 at 11:11:45AM +0800, lin zuojian wrote:
> > Without aligning the asan stack base,this base will only 64-bit aligned in
> > ARM machines.
> > But asan require 256-bit aligned base because of this:
> > 1.right shif
On Tue, Mar 04, 2014 at 11:11:45AM +0800, lin zuojian wrote:
> Without aligning the asan stack base,this base will only 64-bit aligned in
> ARM machines.
> But asan require 256-bit aligned base because of this:
> 1.right shift take ASAN_SHADOW_SHIFT(which is 3) bits are zeros
> 2.store multiple/lo
Hi,
This patch removes trailing whitespaces.
--
Regards
lin zuojian
--
Without aligning the asan stack base,this base will only 64-bit aligned in ARM
machines.
But asan require 256-bit aligned base because of this:
1.right shift take ASAN_SHADOW_SHIFT(which is 3) bits are zeros
2.store multi
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