On Tue, Mar 04, 2014 at 11:11:45AM +0800, lin zuojian wrote:
> Without aligning the asan stack base,this base will only 64-bit aligned in
> ARM machines.
> But asan require 256-bit aligned base because of this:
> 1.right shift take ASAN_SHADOW_SHIFT(which is 3) bits are zeros
> 2.store multiple/load multiple instructions require the other 2 bits are zeros
>
> that add up lowest 5 bits should be zeros.That means 32 bytes or 256 bits
> aligned.
>
> * asan.c (asan_emit_stack_protection): Force the base to align to
> appropriate bits if STRICT_ALIGNMENT. Set shadow_mem align to
> appropriate bits if STRICT_ALIGNMENT.
> * cfgexpand.c (expand_stack_vars): Set base_align appropriately
> when asan is on.
> (expand_used_vars): Leave a space in the stack frame for alignment if
> STRICT_ALIGNMENT.
There were still a couple of formatting issues, I've fixed them below.
Now, do you have a GCC copyright assignment or are under copyright
assignment of some company working on GCC (ARM?)?
2014-03-03 Lin Zuojian <manjian2...@gmail.com>
PR middle-end/60281
* asan.c (asan_emit_stack_protection): Force the base to align to
appropriate bits if STRICT_ALIGNMENT. Set shadow_mem align to
appropriate bits if STRICT_ALIGNMENT.
* cfgexpand.c (expand_stack_vars): Set base_align appropriately
when asan is on.
(expand_used_vars): Leave a space in the stack frame for alignment
if STRICT_ALIGNMENT.
--- gcc/asan.c.jj 2014-01-09 19:09:45.981593894 +0100
+++ gcc/asan.c 2014-03-04 08:55:22.239816211 +0100
@@ -1017,8 +1017,17 @@ asan_emit_stack_protection (rtx base, rt
base_align_bias = ((asan_frame_size + alignb - 1)
& ~(alignb - HOST_WIDE_INT_1)) - asan_frame_size;
}
+ /* Align base if target is STRICT_ALIGNMENT. */
+ if (STRICT_ALIGNMENT)
+ base = expand_binop (Pmode, and_optab, base,
+ gen_int_mode (-((GET_MODE_ALIGNMENT (SImode)
+ << ASAN_SHADOW_SHIFT)
+ / BITS_PER_UNIT), Pmode), NULL_RTX,
+ 1, OPTAB_DIRECT);
+
if (use_after_return_class == -1 && pbase)
emit_move_insn (pbase, base);
+
base = expand_binop (Pmode, add_optab, base,
gen_int_mode (base_offset - base_align_bias, Pmode),
NULL_RTX, 1, OPTAB_DIRECT);
@@ -1097,6 +1106,8 @@ asan_emit_stack_protection (rtx base, rt
&& (ASAN_RED_ZONE_SIZE >> ASAN_SHADOW_SHIFT) == 4);
shadow_mem = gen_rtx_MEM (SImode, shadow_base);
set_mem_alias_set (shadow_mem, asan_shadow_set);
+ if (STRICT_ALIGNMENT)
+ set_mem_align (shadow_mem, (GET_MODE_ALIGNMENT (SImode)));
prev_offset = base_offset;
for (l = length; l; l -= 2)
{
@@ -1186,6 +1197,10 @@ asan_emit_stack_protection (rtx base, rt
shadow_mem = gen_rtx_MEM (BLKmode, shadow_base);
set_mem_alias_set (shadow_mem, asan_shadow_set);
+
+ if (STRICT_ALIGNMENT)
+ set_mem_align (shadow_mem, (GET_MODE_ALIGNMENT (SImode)));
+
prev_offset = base_offset;
last_offset = base_offset;
last_size = 0;
--- gcc/cfgexpand.c.jj 2014-03-03 08:25:17.164537912 +0100
+++ gcc/cfgexpand.c 2014-03-04 08:57:53.860949703 +0100
@@ -1013,10 +1013,19 @@ expand_stack_vars (bool (*pred) (size_t)
if (data->asan_base == NULL)
data->asan_base = gen_reg_rtx (Pmode);
base = data->asan_base;
+
+ if (!STRICT_ALIGNMENT)
+ base_align = crtl->max_used_stack_slot_alignment;
+ else
+ base_align = MAX (crtl->max_used_stack_slot_alignment,
+ GET_MODE_ALIGNMENT (SImode)
+ << ASAN_SHADOW_SHIFT);
}
else
- offset = alloc_stack_frame_space (stack_vars[i].size, alignb);
- base_align = crtl->max_used_stack_slot_alignment;
+ {
+ offset = alloc_stack_frame_space (stack_vars[i].size, alignb);
+ base_align = crtl->max_used_stack_slot_alignment;
+ }
}
else
{
@@ -1843,6 +1852,11 @@ expand_used_vars (void)
= alloc_stack_frame_space (redzonesz, ASAN_RED_ZONE_SIZE);
data.asan_vec.safe_push (prev_offset);
data.asan_vec.safe_push (offset);
+ /* Leave space for alignment if STRICT_ALIGNMENT. */
+ if (STRICT_ALIGNMENT)
+ alloc_stack_frame_space ((GET_MODE_ALIGNMENT (SImode)
+ << ASAN_SHADOW_SHIFT)
+ / BITS_PER_UNIT, 1);
var_end_seq
= asan_emit_stack_protection (virtual_stack_vars_rtx,
Jakub
