: juzhe.zh...@rivai.ai; gcc-patches
CC: kito.cheng; Jeff Law
Subject: Re: Re: [PATCH v4 2/3] RISC-V: Add crypto machine descriptions
2023-12-20 15:12 juzhe.zhong wrote:
>+ (and:VI
>+ (match_operand:VI 3 "register_operand" "vr, vr, vr, vr")
>+
2023-12-20 15:12 juzhe.zhong wrote:
>+ (and:VI
>+ (match_operand:VI 3 "register_operand" "vr, vr, vr, vr")
>+ (not:VI (match_operand:VI 4 "register_operand" "vr, vr, vr, vr")))
>Swap the order:
>
>(not:VI (match_operand:VI 4 "register_operand" "vr, vr, vr, vr")
>
r,vr, vr"))
Can you add EEW64 vx test on RV32 ?
juzhe.zh...@rivai.ai
From: Feng Wang
Date: 2023-12-20 15:05
To: gcc-patches
CC: kito.cheng; jeffreyalaw; juzhe.zhong; Feng Wang
Subject: [PATCH v4 2/3] RISC-V: Add crypto machine descriptions
Patch v4: Add process of SEW=64 in RV32 system.
Pat
Patch v4: Add process of SEW=64 in RV32 system.
Patch v3: Moidfy constrains for crypto vector.
Patch v2: Add crypto vector ins into RATIO attr and use vr as
destination register.
This patch add the crypto machine descriptions(vector-crypto.md) and
some new iterators which are used by crypto vector
