-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; rdapp@gmail.com
Subject: Re: [PATCH v2] RISC-V: Support IMM for operand 0 of ussub pattern
On 8/13/24 9:47 PM, Li, Pan2 wrote:
>>> +static rtx
>>> +riscv_gen_unsigned_xmode_reg (rtx x, machine_mode mode)
>
On 8/13/24 9:47 PM, Li, Pan2 wrote:
+static rtx
+riscv_gen_unsigned_xmode_reg (rtx x, machine_mode mode)
+{
+ if (!CONST_INT_P (x))
+return gen_lowpart (Xmode, x);
+
+ rtx xmode_x = gen_reg_rtx (Xmode);
+ HOST_WIDE_INT cst = INTVAL (x);
+
+ emit_move_insn (xmode_x, x);
+
+ int xmode_b
given the incoming rtx x is
const_int which is DImode(integer promoted)
for ussub.
I will rebase this patch after PR116278 commit, and give a try for this.
Pan
-Original Message-
From: Jeff Law
Sent: Wednesday, August 14, 2024 11:33 AM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.
;
rdapp@gmail.com; Li, Pan2
Subject: [PATCH v2] RISC-V: Support IMM for operand 0 of ussub pattern
From: Pan Li
This patch would like to allow IMM for the operand 0 of ussub pattern.
Aka .SAT_SUB(1023, y) as the below example.
Form 1:
#define DEF_SAT_U_SUB_IMM_FMT_1(T, IMM) \
T
: [PATCH v2] RISC-V: Support IMM for operand 0 of ussub pattern
From: Pan Li
This patch would like to allow IMM for the operand 0 of ussub pattern.
Aka .SAT_SUB(1023, y) as the below example.
Form 1:
#define DEF_SAT_U_SUB_IMM_FMT_1(T, IMM) \
T __attribute__((noinline
From: Pan Li
This patch would like to allow IMM for the operand 0 of ussub pattern.
Aka .SAT_SUB(1023, y) as the below example.
Form 1:
#define DEF_SAT_U_SUB_IMM_FMT_1(T, IMM) \
T __attribute__((noinline)) \
sat_u_sub_imm##IMM##_##T##_fmt_1 (T y) \
{
