On 1/13/25 1:41 AM, Jin Ma wrote:
Thank you very much for your professional reply. I am trying to solve the
problem
using the "spec_restriction" way. But unfortunately, I have a new problem. As
pattern below, how can I enable "r" and disable "K" when XTheadVector? "rK"
already
seems to be th
> Yes. This will solve the problem, but it will lead to very large-scale changes
> (splitting each rK, adding 1 column constraint), and make the pattern more
> complex
> and more difficult to maintain. In contrast, how about replacing "rK" with a
> new
> constrain in the way jeff mentioned? For e
> > Thank you very much for your professional reply. I am trying to solve the
> > problem
> > using the "spec_restriction" way. But unfortunately, I have a new problem.
> > As
> > pattern below, how can I enable "r" and disable "K" when XTheadVector? "rK"
> > already
> > seems to be the smallest
> Thank you very much for your professional reply. I am trying to solve the
> problem
> using the "spec_restriction" way. But unfortunately, I have a new problem. As
> pattern below, how can I enable "r" and disable "K" when XTheadVector? "rK"
> already
> seems to be the smallest unit and not abl
> > Looking at the log for the reload pass, it is found that "Changing pseudo
> > 209
> > in operand 3 of insn 69 on equiv 0x 1". It converts the vl operand in insn
> > from the expected register(reg:DI 209) to the constant 1(const_int 1 [0x1]).
> >
> > This conversion occurs because, although the
On 12/17/24 5:05 AM, Jin Ma wrote:
I missed some information because of the long time.
Happens to me all the time ;-)
As I said before, instead of using UNSPEC, In the curr_insn_transform function,
the insn is transformed from:
(insn 69 67 225 12 (set (mem:RVVM8SF (reg/f:DI 218 [ _77 ]
> Looking at the log for the reload pass, it is found that "Changing pseudo 209
> in operand 3 of insn 69 on equiv 0x 1". It converts the vl operand in insn
> from the expected register(reg:DI 209) to the constant 1(const_int 1 [0x1]).
>
> This conversion occurs because, although the predicate for
> > --- a/gcc/config/riscv/riscv-vector-builtins.cc
> > +++ b/gcc/config/riscv/riscv-vector-builtins.cc
> > @@ -4089,7 +4089,23 @@ function_expander::add_input_operand (unsigned argno)
> > {
> > tree arg = CALL_EXPR_ARG (exp, argno);
> > rtx x = expand_normal (arg);
> > - add_input_opera
> So I would just do:
>
>
> tmp = force_reg (word_mode, x);
> add_input_operand (TYPE_MODE (TREE_TYPE (arg)), tmp);
>
> In the thead specific code. That generates the initial code correctly.
> At that point we just need to make sure nothing like combine, cprop, etc
> propagates the constant into
On 12/2/24 11:34 PM, Jin Ma wrote:
Since XTheadvector does not support vsetivli, vl needs to be put into
registers during the expand phase.
PR 116593
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins.cc
(function_expander::add_input_operand):
Put const to GPR for
Since XTheadvector does not support vsetivli, vl needs to be put into
registers during the expand phase.
PR 116593
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins.cc
(function_expander::add_input_operand):
Put const to GPR for vl.
* config/riscv/thead-vector.
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