On 12/17/24 5:05 AM, Jin Ma wrote:
I missed some information because of the long time.
Happens to me all the time ;-)
As I said before, instead of using UNSPEC, In the curr_insn_transform function,
the insn is transformed from:
(insn 69 67 225 12 (set (mem:RVVM8SF (reg/f:DI 218 [ _77 ]) [0 S[128, 128]
A32])
(if_then_else:RVVM8SF (unspec:RVVMF4BI [
(const_vector:RVVMF4BI repeat [
(const_int 1 [0x1])
])
(reg:DI 209)
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(reg/v:RVVM8SF 143 [ _xx ])
(mem:RVVM8SF (reg/f:DI 218 [ _77 ]) [0 S[128, 128] A32])))
"pr116593.C":14:24 discrim 1 3883 {pred_storervvm8sf}
(expr_list:REG_DEAD (reg/v:RVVM8SF 143 [ _xx ])
(nil)))
to
(insn 69 284 225 11 (set (mem:RVVM8SF (reg/f:DI 18 s2 [orig:218 _77 ] [218]) [0
S[128, 128] A32])
(if_then_else:RVVM8SF (unspec:RVVMF4BI [
(const_vector:RVVMF4BI repeat [
(const_int 1 [0x1])
])
(const_int 1 [0x1])
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(reg/v:RVVM8SF 104 v8 [orig:143 _xx ] [143])
(mem:RVVM8SF (reg/f:DI 18 s2 [orig:218 _77 ] [218]) [0 S[128, 128] A32])))
"pr116593.C":14:24 discrim 1 3883 {pred_storervvm8sf}
(nil))
Looking at the log for the reload pass, it is found that "Changing pseudo 209 in
operand 3 of insn 69 on equiv 0x 1".
It converts the vl operand in insn from the expected register(reg:DI 209) to
the constant 1(const_int 1 [0x1]).
OK. This is where we need to focus.
This conversion occurs because, although the predicate for the vl operand is restricted
by "vector_length_operand" in the pattern,
the constraint is still "rK", which allows the transformation.
That's a bit odd, I would have expected the predicate to be checked, but
sometimes things are "odd" in reload.
The issue is that changing the "rK" constraint to "rJ" for the constraint of vl
operand in the pattern would prevent this conversion,
But unfortunately this will conflict with RVV (RISC-V Vector Extension).
This is why I initially considered using UNSPEC to address the XTheadVector
problem while minimizing interference with RVV.
I'm not sure if there is a better way, do you have any suggestions?
I think Robin mentioned disabling certain alternatives which is one
approach (I've never used that capability, but I know it exists and this
would be a pretty good fit). For this approach I'd suggest disabling
the rK alternative for thead-vector and (if we don't have it) adding an
alternative that only accepts a register.
We could also create a new constraint that mostly behaves like rK, but
rejects (const_int 1) when thead-vector is enabled and use that in the
vsetvl pattern instead of rK.
The brute force, but least favorite, approach would be to create two
distinct patterns, one for thead the other for rvv. Obviously the thead
pattern would use different constraints to prevent replacing registers
with constants.
Jeff
Jeff
