On Sat, 12 Mar 2022, Xi Ruoyao via Gcc-patches wrote:
> I'm now thinking: is there always at least one *GPR* which need to be
> cleared? If it's true, let's say GPR $12, and fcc0 & fcc2 needs to be
> cleared, we can use something like:
>
> cfc1 $12, $25
> andi $25, 5
> ctc1 $12, $25
> move $12,
> On Mar 18, 2022, at 11:09 AM, Richard Sandiford
> wrote:
>
> Xi Ruoyao writes:
>>>
>>> If we have to go this way, I think it’s better to make the change you
>>> suggested above,
>>> and then also update the documentation, both internal documentation on
>>> how to define
>>> the hook and
Xi Ruoyao writes:
>>
>> If we have to go this way, I think it’s better to make the change you
>> suggested above,
>> and then also update the documentation, both internal documentation on
>> how to define
>> the hook and the user level documentation on what the user might
>> expect when using
>
> If we have to go this way, I think it’s better to make the change you
> suggested above,
> and then also update the documentation, both internal documentation on
> how to define
> the hook and the user level documentation on what the user might
> expect when using
> this option (i.e, it’s
> On Mar 14, 2022, at 11:04 AM, Richard Sandiford
> wrote:
>
> Sorry for the slow response, was out for a few days.
>
> Xi Ruoyao writes:
>> On Sat, 2022-03-12 at 18:48 +0800, Xi Ruoyao via Gcc-patches wrote:
>>> On Fri, 2022-03-11 at 21:26 +, Qing Zhao wrote:
Hi, Ruoyao,
On Mon, 2022-03-14 at 16:04 +, Richard Sandiford wrote:
> Xi Ruoyao writes:
> > Now I think the only rational ways are:
> >
> > (1) allow zeroing more registers than need_zeroed_hardregs.
>
> I think this is the way to go. I agree it's a bit hacky, but it seems
> like the least worst opti
Sorry for the slow response, was out for a few days.
Xi Ruoyao writes:
> On Sat, 2022-03-12 at 18:48 +0800, Xi Ruoyao via Gcc-patches wrote:
>> On Fri, 2022-03-11 at 21:26 +, Qing Zhao wrote:
>> > Hi, Ruoyao,
>> >
>> > (I might not be able to reply to this thread till next Wed due to a
>> >
On Sat, 2022-03-12 at 18:48 +0800, Xi Ruoyao via Gcc-patches wrote:
> On Fri, 2022-03-11 at 21:26 +, Qing Zhao wrote:
> > Hi, Ruoyao,
> >
> > (I might not be able to reply to this thread till next Wed due to a
> > short vacation).
> >
> > First, some comments on opening bugs against Gcc:
> >
On Fri, 2022-03-11 at 21:26 +, Qing Zhao wrote:
> Hi, Ruoyao,
>
> (I might not be able to reply to this thread till next Wed due to a
> short vacation).
>
> First, some comments on opening bugs against Gcc:
>
> I took a look at the bug reports PR104817 and PR104820:
> https://gcc.gnu.org/bug
Hi, Ruoyao,
(I might not be able to reply to this thread till next Wed due to a short
vacation).
First, some comments on opening bugs against Gcc:
I took a look at the bug reports PR104817 and PR104820:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104820
https://gcc.gnu.org/bugzilla/show_bug.cg
On Sat, 2022-03-12 at 01:29 +0800, Xi Ruoyao via Gcc-patches wrote:
> I'm now thinking: is there always at least one *GPR* which need to be
> cleared? If it's true, let's say GPR $12, and fcc0 & fcc2 needs to be
> cleared, we can use something like:
>
> cfc1 $12, $25
> andi $25, 5
$12, 5.
I ca
On Fri, 2022-03-11 at 16:08 +, Qing Zhao wrote:
> Why there is “mthi $0” instruction, but there is NO emit_move_insn(HI,
> CONST_0)?
> Is such mismatch a bug? If not, why?
>
> > In theory it's possible
> > to emit the mthi instruction explicitly here though, but we'll need to
> > clear som
> On Mar 10, 2022, at 8:54 PM, Xi Ruoyao wrote:
>
> On Thu, 2022-03-10 at 20:31 +, Qing Zhao wrote:
>
+ SET_HARD_REG_BIT (zeroed_hardregs, HI_REGNUM);
+ if (TEST_HARD_REG_BIT (need_zeroed_hardregs, LO_REGNUM))
+ SET_HARD_REG_BIT (zeroed_hardregs, LO_REGNUM);
On Thu, 2022-03-10 at 20:31 +, Qing Zhao wrote:
> > > + SET_HARD_REG_BIT (zeroed_hardregs, HI_REGNUM);
> > > + if (TEST_HARD_REG_BIT (need_zeroed_hardregs, LO_REGNUM))
> > > + SET_HARD_REG_BIT (zeroed_hardregs, LO_REGNUM);
> > > + else
> > > + emit_clobber (gen_rtx_R
> On Mar 9, 2022, at 12:25 PM, Richard Sandiford via Gcc-patches
> wrote:
>
> Xi Ruoyao writes:
>> Bootstrapped and regtested on mips64el-linux-gnuabi64.
>>
>> I'm not sure if it's "correct" to clobber other registers during the
>> zeroing of scratch registers. But I can't really come up wi
On Wed, 2022-03-09 at 18:25 +, Richard Sandiford wrote:
> Xi Ruoyao writes:
> > Bootstrapped and regtested on mips64el-linux-gnuabi64.
> >
> > I'm not sure if it's "correct" to clobber other registers during the
> > zeroing of scratch registers. But I can't really come up with a
> > better
>
Xi Ruoyao writes:
> Bootstrapped and regtested on mips64el-linux-gnuabi64.
>
> I'm not sure if it's "correct" to clobber other registers during the
> zeroing of scratch registers. But I can't really come up with a better
> idea: on MIPS there is no simple way to clear one bit in FCSR (i. e.
> FCC
Bootstrapped and regtested on mips64el-linux-gnuabi64.
I'm not sure if it's "correct" to clobber other registers during the
zeroing of scratch registers. But I can't really come up with a better
idea: on MIPS there is no simple way to clear one bit in FCSR (i. e.
FCC[x]). We can't just use "c.f.
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