:
> > __mm256.*__;
> > #else
> > __mm512.*__;
> > #endif
> >
> > If we understand correctly, we'll consider the request. But since we're
> > about to have a vacation, follow-up replies may be a bit slower.
> >
> > BRs,
> >
rsday, September 28, 2023 8:32 AM
To: Hu, Lin1 ; gcc-patches@gcc.gnu.org
Subject: Re: [PATCH 00/18] Support -mevex512 for AVX512
Thanks for the new patch!
I see that there's a new __EVEX512__ define. Will there be some __EVEX256__
(or maybe some max EVEX width) define, so that code can detect
Subject: Re: [PATCH 00/18] Support -mevex512 for AVX512
Thanks for the new patch!
I see that there's a new __EVEX512__ define. Will there be some __EVEX256__
(or maybe some max EVEX width) define, so that code can detect whether the
compiler supports AVX10.1/256 without resorting to version checks?
Thanks for the new patch!
I see that there's a new __EVEX512__ define. Will there be some
__EVEX256__ (or maybe some max EVEX width) define, so that code can
detect whether the compiler supports AVX10.1/256 without resorting to
version checks?
On Thu, Sep 21, 2023 at 3:22 PM Hu, Lin1 wrote:
>
> Hi all,
>
> After previous discussion, instead of supporting option -mavx10.1, we
> will first introduct option -m[no-]evex512, which will enable/disable
> 512 bit register and 64 bit mask register.
>
> It will not change the current option behav
Hi all,
After previous discussion, instead of supporting option -mavx10.1, we
will first introduct option -m[no-]evex512, which will enable/disable
512 bit register and 64 bit mask register.
It will not change the current option behavior since if AVX512F is
enabled with no evex512 option specifie
