Re: [PATCH 0/2] RISC-V: Add ldr/str instruction for T-HEAD.

2021-07-13 Thread Palmer Dabbelt
On Sat, 10 Jul 2021 19:31:20 PDT (-0700), gcc-patches@gcc.gnu.org wrote: Hi, Ping. @Jim @kito — Jojo 在 2021年7月9日 +0800 AM9:30，ALO ，写道： Hi, Ping. — Jojo 在 2021年6月29日 +0800 PM4:11，Jojo R ，写道： > T-HEAD extends some customized ISAs for Cores. > The patches support ldr/str

Re: [PATCH 0/2] RISC-V: Add ldr/str instruction for T-HEAD.

2021-07-10 Thread ALO via Gcc-patches
Hi, Ping. @Jim @kito — Jojo 在 2021年7月9日 +0800 AM9:30，ALO ，写道： > Hi, > Ping. > > — Jojo > 在 2021年6月29日 +0800 PM4:11，Jojo R ，写道： > > T-HEAD extends some customized ISAs for Cores. > > The patches support ldr/str insns, it likes arm's LDR insn, the > > memory model is a base r

Re: [PATCH 0/2] RISC-V: Add ldr/str instruction for T-HEAD.

2021-07-08 Thread ALO via Gcc-patches
Hi, Ping. — Jojo 在 2021年6月29日 +0800 PM4:11，Jojo R ，写道： > T-HEAD extends some customized ISAs for Cores. > The patches support ldr/str insns, it likes arm's LDR insn, the > memory model is a base register indexed by (optionally scaled) register.

[PATCH 0/2] RISC-V: Add ldr/str instruction for T-HEAD.

2021-06-29 Thread Jojo R via Gcc-patches
T-HEAD extends some customized ISAs for Cores. The patches support ldr/str insns, it likes arm's LDR insn, the memory model is a base register indexed by (optionally scaled) register.