On Tue, Aug 22, 2023 at 5:05 PM Richard Biener via Gcc-patches
wrote:
>
> The PRs ask for optimizing of
>
> _1 = BIT_FIELD_REF ;
> result_4 = BIT_INSERT_EXPR ;
>
> to a vector permutation. The following implements this as
> match.pd pattern, improving code generation on x86_64.
>
> On the RTL
The PRs ask for optimizing of
_1 = BIT_FIELD_REF ;
result_4 = BIT_INSERT_EXPR ;
to a vector permutation. The following implements this as
match.pd pattern, improving code generation on x86_64.
On the RTL level we face the issue that backend patterns inconsistently
use vec_merge and vec_sele
On Sat, Jul 15, 2023 at 10:31 AM Andrew Pinski wrote:
>
> On Wed, Jul 12, 2023 at 6:37 AM Richard Biener via Gcc-patches
> wrote:
> >
> > The PRs ask for optimizing of
> >
> > _1 = BIT_FIELD_REF ;
> > result_4 = BIT_INSERT_EXPR ;
> >
> > to a vector permutation. The following implements this
On Wed, Jul 12, 2023 at 6:37 AM Richard Biener via Gcc-patches
wrote:
>
> The PRs ask for optimizing of
>
> _1 = BIT_FIELD_REF ;
> result_4 = BIT_INSERT_EXPR ;
>
> to a vector permutation. The following implements this as
> match.pd pattern, improving code generation on x86_64.
This is more
On Thu, Jul 13, 2023 at 2:32 PM Richard Biener wrote:
>
> On Thu, 13 Jul 2023, Hongtao Liu wrote:
>
> > On Thu, Jul 13, 2023 at 10:47?AM Hongtao Liu wrote:
> > >
> > > On Wed, Jul 12, 2023 at 9:37?PM Richard Biener via Gcc-patches
> > > wrote:
> > > >
> > > > The PRs ask for optimizing of
> > >
On Wed, 12 Jul 2023, Richard Sandiford wrote:
> Richard Biener writes:
> > The PRs ask for optimizing of
> >
> > _1 = BIT_FIELD_REF ;
> > result_4 = BIT_INSERT_EXPR ;
> >
> > to a vector permutation. The following implements this as
> > match.pd pattern, improving code generation on x86_64.
On Thu, 13 Jul 2023, Hongtao Liu wrote:
> On Thu, Jul 13, 2023 at 10:47?AM Hongtao Liu wrote:
> >
> > On Wed, Jul 12, 2023 at 9:37?PM Richard Biener via Gcc-patches
> > wrote:
> > >
> > > The PRs ask for optimizing of
> > >
> > > _1 = BIT_FIELD_REF ;
> > > result_4 = BIT_INSERT_EXPR ;
> > >
On Thu, Jul 13, 2023 at 10:47 AM Hongtao Liu wrote:
>
> On Wed, Jul 12, 2023 at 9:37 PM Richard Biener via Gcc-patches
> wrote:
> >
> > The PRs ask for optimizing of
> >
> > _1 = BIT_FIELD_REF ;
> > result_4 = BIT_INSERT_EXPR ;
> >
> > to a vector permutation. The following implements this a
On Wed, Jul 12, 2023 at 9:37 PM Richard Biener via Gcc-patches
wrote:
>
> The PRs ask for optimizing of
>
> _1 = BIT_FIELD_REF ;
> result_4 = BIT_INSERT_EXPR ;
>
> to a vector permutation. The following implements this as
> match.pd pattern, improving code generation on x86_64.
>
> On the RTL
Richard Biener writes:
> The PRs ask for optimizing of
>
> _1 = BIT_FIELD_REF ;
> result_4 = BIT_INSERT_EXPR ;
>
> to a vector permutation. The following implements this as
> match.pd pattern, improving code generation on x86_64.
>
> On the RTL level we face the issue that backend patterns in
On 7/12/23 07:36, Richard Biener via Gcc-patches wrote:
The PRs ask for optimizing of
_1 = BIT_FIELD_REF ;
result_4 = BIT_INSERT_EXPR ;
to a vector permutation. The following implements this as
match.pd pattern, improving code generation on x86_64.
On the RTL level we face the issue
The PRs ask for optimizing of
_1 = BIT_FIELD_REF ;
result_4 = BIT_INSERT_EXPR ;
to a vector permutation. The following implements this as
match.pd pattern, improving code generation on x86_64.
On the RTL level we face the issue that backend patterns inconsistently
use vec_merge and vec_sele
12 matches
Mail list logo
