On Mon, Aug 12, 2024 at 08:48:22AM -0500, Peter Bergner wrote:
> On 8/11/24 9:42 PM, Kewen.Lin wrote:
> > One difference with this change is that previously users specify -mno-vsx to
> > disable all vector insns (both VMX and VSX) on Power[89], now they should
> > use -mno-altivec for that purpose.
Hi!
On Mon, Aug 12, 2024 at 10:42:48AM +0800, Kewen.Lin wrote:
> on 2024/8/10 05:43, Segher Boessenkool wrote:
> IIUC, we want to split TARGET_P[89]_VECTOR into TARGET_P[89]_ALTIVEC and
> TARGET_P[89]_VSX (or just TARGET_POWER[89] && TARGET_VSX or TARGET_ALTIVEC)
> according to the context (VMX or
On 8/11/24 9:42 PM, Kewen.Lin wrote:
> One difference with this change is that previously users specify -mno-vsx to
> disable all vector insns (both VMX and VSX) on Power[89], now they should
> use -mno-altivec for that purpose. I think it's better as it matches the
> behaviors on Power7?
I hope
On 8/9/24 4:43 PM, Segher Boessenkool wrote:
> On Fri, Aug 09, 2024 at 03:50:50PM -0500, Peter Bergner wrote:
>> I'm fine with the TARGET_P10_* macro, since it's more readable than saying
>> TARGET_POWER10 && TARGET_ALTIVEC && TARGET_VSX, especially when we use the
>> negated version.
>
> It is no
Hi Segher & Peter,
Thanks for your comments!!
on 2024/8/10 05:43, Segher Boessenkool wrote:
> On Fri, Aug 09, 2024 at 03:50:50PM -0500, Peter Bergner wrote:
>> On 8/9/24 12:54 PM, Segher Boessenkool wrote:
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -62
On Fri, Aug 09, 2024 at 03:50:50PM -0500, Peter Bergner wrote:
> On 8/9/24 12:54 PM, Segher Boessenkool wrote:
> >> --- a/gcc/config/rs6000/altivec.md
> >> +++ b/gcc/config/rs6000/altivec.md
> >> @@ -623,7 +623,7 @@ (define_insn "altivec_eqv1ti"
> >>[(set (match_operand:V1TI 0 "altivec_register
On 8/9/24 12:54 PM, Segher Boessenkool wrote:
>> --- a/gcc/config/rs6000/altivec.md
>> +++ b/gcc/config/rs6000/altivec.md
>> @@ -623,7 +623,7 @@ (define_insn "altivec_eqv1ti"
>>[(set (match_operand:V1TI 0 "altivec_register_operand" "=v")
>> (eq:V1TI (match_operand:V1TI 1 "altivec_register
Hi!
On Fri, Aug 09, 2024 at 05:50:18PM +0800, Kewen.Lin wrote:
> As PR116266 shows, we miss TARGET_P10_VECTOR to guard those
> Power10 related vector instructions as well as their
> according built-in functions. This patch is to introduce
> TARGET_P10_VECTOR which is actually TARGET_POWER10 &&
>
On 8/9/24 4:50 AM, Kewen.Lin wrote:
> As PR116266 shows, we miss TARGET_P10_VECTOR to guard those
> Power10 related vector instructions as well as their
> according built-in functions. This patch is to introduce...
LGTM.
The only change I would suggest is s/according/associated/ in
the sentence
Hi,
As PR116266 shows, we miss TARGET_P10_VECTOR to guard those
Power10 related vector instructions as well as their
according built-in functions. This patch is to introduce
TARGET_P10_VECTOR which is actually TARGET_POWER10 &&
TARGET_VSX underlying, it updates many places that should
adopt TARGE
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