Hi! On Fri, Aug 09, 2024 at 05:50:18PM +0800, Kewen.Lin wrote: > As PR116266 shows, we miss TARGET_P10_VECTOR to guard those > Power10 related vector instructions as well as their > according built-in functions. This patch is to introduce > TARGET_P10_VECTOR which is actually TARGET_POWER10 && > TARGET_VSX underlying, it updates many places that should > adopt TARGET_P10_VECTOR rather than TARGET_POWER10.
Why do we want this at all? Can't people just say what they mean? > --- a/gcc/config/rs6000/altivec.md > +++ b/gcc/config/rs6000/altivec.md > @@ -623,7 +623,7 @@ (define_insn "altivec_eqv1ti" > [(set (match_operand:V1TI 0 "altivec_register_operand" "=v") > (eq:V1TI (match_operand:V1TI 1 "altivec_register_operand" "v") > (match_operand:V1TI 2 "altivec_register_operand" "v")))] > - "TARGET_POWER10" > + "TARGET_P10_VECTOR" > "vcmpequq %0,%1,%2" > [(set_attr "type" "veccmpfx")]) This very first one is incorrect, already. This is a Vector insn (it needs MSR[VEC]=1), not a VSX insn (for which MSR[VSX]=1 is needed). We test TARGET_ALTIVEC for that, not TARGET_VSX. In general, we want to get rid of TARGET_Pxxx_VECTOR, not introduce new stuff like it! Segher
