On Fri, Mar 12, 2021 at 11:56 PM Jakub Jelinek wrote:
>
> On Fri, Mar 12, 2021 at 07:52:16PM +0100, Uros Bizjak via Gcc-patches wrote:
> > > I can test it on avx512{bw,vl,dq} hw tonight if you want.
> >
> > I'm testing the patch on avx2 hw, which is not representative of this
> > change. So if you
On Fri, Mar 12, 2021 at 07:52:16PM +0100, Uros Bizjak via Gcc-patches wrote:
> > I can test it on avx512{bw,vl,dq} hw tonight if you want.
>
> I'm testing the patch on avx2 hw, which is not representative of this
> change. So if you can spare a few cycles, that would be awesome.
Passed bootstrap/
V pet., 12. mar. 2021 19:19 je oseba Jakub Jelinek napisala:
>
> On Fri, Mar 12, 2021 at 06:48:57PM +0100, Uros Bizjak wrote:
> > It is hidden in *vec_extractv4si pattern:
> >
> > (define_insn "*vec_extractv4si"
> > - [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm,Yr,*x,x,Yv")
> > + [
On Fri, Mar 12, 2021 at 06:48:57PM +0100, Uros Bizjak wrote:
> It is hidden in *vec_extractv4si pattern:
>
> (define_insn "*vec_extractv4si"
> - [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm,Yr,*x,x,Yv")
> + [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm,Yr,*x,Yw")
> (
On Fri, Mar 12, 2021 at 6:32 PM Jakub Jelinek wrote:
>
> On Fri, Mar 12, 2021 at 06:05:34PM +0100, Uros Bizjak wrote:
> > Untested patch that introduces YW to some remaining pextr
> > instructions, fixes one case of 128bit vpsrldq and 128bit vpalignr w/o
> > AVX512VL.
>
> Not sure I can find the v
On Fri, Mar 12, 2021 at 06:05:34PM +0100, Uros Bizjak wrote:
> Untested patch that introduces YW to some remaining pextr
> instructions, fixes one case of 128bit vpsrldq and 128bit vpalignr w/o
> AVX512VL.
Not sure I can find the vpsrldq change in there.
> @@ -21599,11 +21590,11 @@
> (set_att
On Fri, Mar 12, 2021 at 5:11 PM Uros Bizjak wrote:
>
> On Fri, Mar 12, 2021 at 4:28 PM Jakub Jelinek wrote:
> >
> > On Fri, Mar 12, 2021 at 03:34:09PM +0100, Uros Bizjak wrote:
> > > > (define_insn "*avx2_pmaddwd"
> > > > - [(set (match_operand:V8SI 0 "register_operand" "=x,v")
> > > > + [(set
On Fri, Mar 12, 2021 at 4:28 PM Jakub Jelinek wrote:
>
> On Fri, Mar 12, 2021 at 03:34:09PM +0100, Uros Bizjak wrote:
> > > (define_insn "*avx2_pmaddwd"
> > > - [(set (match_operand:V8SI 0 "register_operand" "=x,v")
> > > + [(set (match_operand:V8SI 0 "register_operand" "=Yw")
> >
> > I'm not s
On Fri, Mar 12, 2021 at 03:34:09PM +0100, Uros Bizjak wrote:
> > (define_insn "*avx2_pmaddwd"
> > - [(set (match_operand:V8SI 0 "register_operand" "=x,v")
> > + [(set (match_operand:V8SI 0 "register_operand" "=Yw")
>
> I'm not sure contraction like this is correct. The prolbem is with vex
> vs.
On Fri, Mar 12, 2021 at 2:38 PM Jakub Jelinek wrote:
>
> On Fri, Mar 12, 2021 at 09:35:00AM +0100, Uros Bizjak via Gcc-patches wrote:
> > Perhaps we can introduce another Y... constraint for AVX512BW and use
> > it here. I think they will be used in other places, too.
>
> Ok, added YW constraint a
On Fri, Mar 12, 2021 at 09:35:00AM +0100, Uros Bizjak via Gcc-patches wrote:
> Perhaps we can introduce another Y... constraint for AVX512BW and use
> it here. I think they will be used in other places, too.
Ok, added YW constraint and used that for those mmx*{ins,ext}* as well
as _psadbw.
Here i
On Fri, Mar 12, 2021 at 8:59 AM Jakub Jelinek wrote:
>
> Hi!
>
> This is the final patch of the series started with
> https://gcc.gnu.org/pipermail/gcc-patches/2021-March/566139.html
> and continued with
> https://gcc.gnu.org/pipermail/gcc-patches/2021-March/566356.html
> This time, I went through
Hi!
This is the final patch of the series started with
https://gcc.gnu.org/pipermail/gcc-patches/2021-March/566139.html
and continued with
https://gcc.gnu.org/pipermail/gcc-patches/2021-March/566356.html
This time, I went through all the remaining instructions marked
by gas as requiring both AVX51
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