On Fri, Mar 12, 2021 at 11:56 PM Jakub Jelinek <ja...@redhat.com> wrote:
>
> On Fri, Mar 12, 2021 at 07:52:16PM +0100, Uros Bizjak via Gcc-patches wrote:
> > > I can test it on avx512{bw,vl,dq} hw tonight if you want.
> >
> > I'm testing the patch on avx2 hw, which is not representative of this
> > change. So if you can spare a few cycles, that would be awesome.
>
> Passed bootstrap/regtest on both x86_64-linux and i686-linux on i9-7960X.
Thanks, pushed to mainline with the following ChangeLog:
i386: Some more -mavx512vl -mno-avx512bw fixes [PR99321]
2021-03-14 Uroš Bizjak <ubiz...@gmail.com>
gcc/
* config/i386/sse.md (*vec_extract<mode>): Merge alternative 0 with
alternative 2 and alternative 1 with alternative 3 using
YW register constraint.
(*vec_extract<PEXTR_MODE12:mode>_zext): Merge alternatives
using YW register constraint.
(*vec_extractv16qi_zext): Ditto.
(*vec_extractv4si): Merge alternatives 4 and 5
using Yw register constraint.
(*ssse3_palignr<mode>_perm): Use Yw instead of v for alternative 3.
Uros.
