On Mon, Aug 24, 2020 at 6:12 PM Jeff Law wrote:
> On Thu, 2020-08-06 at 12:42 +, Pip Cet via Gcc-patches wrote:
> > I've bootstrapped and run the test suite with the patch, without
> > differences.
> So it looks like Richard has given you some feedback and you've got some
> further
> work to
On Thu, 2020-08-06 at 12:42 +, Pip Cet via Gcc-patches wrote:
> I'm working on the AVR cc0 -> CCmode conversion (bug#92729). One
> problem is that the cmpelim pass is currently very strict in requiring
> insns of the form
>
> (parallel [(set (reg:SI) (op:SI ... ...))
>(clobber (reg
Pip Cet writes:
>> Pip Cet via Gcc-patches writes:
>> > I'm working on the AVR cc0 -> CCmode conversion (bug#92729). One
>> > problem is that the cmpelim pass is currently very strict in requiring
>> > insns of the form
>> >
>> > (parallel [(set (reg:SI) (op:SI ... ...))
>> >(clobber
On Wed, Aug 19, 2020 at 11:05 AM Richard Sandiford
wrote:
> Sorry for the slow reply.
Not a problem at all. Thank you for responding!
> Pip Cet via Gcc-patches writes:
> > I'm working on the AVR cc0 -> CCmode conversion (bug#92729). One
> > problem is that the cmpelim pass is currently very str
Sorry for the slow reply.
Pip Cet via Gcc-patches writes:
> I'm working on the AVR cc0 -> CCmode conversion (bug#92729). One
> problem is that the cmpelim pass is currently very strict in requiring
> insns of the form
>
> (parallel [(set (reg:SI) (op:SI ... ...))
>(clobber (reg:CC REG
I'm working on the AVR cc0 -> CCmode conversion (bug#92729). One
problem is that the cmpelim pass is currently very strict in requiring
insns of the form
(parallel [(set (reg:SI) (op:SI ... ...))
(clobber (reg:CC REG_CC))])
when in fact AVR's insns often have the form
(parallel [(set
