On Thu, 2020-08-06 at 12:42 +0000, Pip Cet via Gcc-patches wrote: > I'm working on the AVR cc0 -> CCmode conversion (bug#92729). One > problem is that the cmpelim pass is currently very strict in requiring > insns of the form > > (parallel [(set (reg:SI) (op:SI ... ...)) > (clobber (reg:CC REG_CC))]) > > when in fact AVR's insns often have the form > > (parallel [(set (reg:SI) (op:SI ... ...)) > (clobber (scratch:QI)) > (clobber (reg:CC REG_CC))]) > > The attached patch relaxes checks in the cmpelim code to recognize > such insns, and makes it attempt to recognize > > (parallel [(set (reg:CC REG_CC) (compare:CC ... ...)) > (set (reg:SI (op:SI ... ...))) > (clobber (scratch:QI))]) > > as a new insn for that example. This appears to work. > > I've bootstrapped and run the test suite with the patch, without differences. So it looks like Richard has given you some feedback and you've got some further work to do. I just wanted to chime in and say thanks for tackling this.
The H8 has similiar problems -- I've fixed them in a different way, but improving cmp-elim is still a good thing. Jeff
