he
operation, like whether it's VMULH or POW ?
Thanks,
Yanzhang
From: juzhe.zh...@rivai.ai
Sent: Wednesday, June 21, 2023 2:33 PM
To: Robin Dapp ; Wang, Yanzhang ;
gcc-patches
Cc: Robin Dapp ; Kito.cheng ; Li,
Pan2
Subject: Re: Re: [PATCH] RISC-V: convert the mulh with 0 to mov 0 to the
: juzhe.zh...@rivai.ai
Sent: Wednesday, June 21, 2023 2:33 PM
To: Robin Dapp ; Wang, Yanzhang ;
gcc-patches
Cc: Robin Dapp ; Kito.cheng ; Li,
Pan2
Subject: Re: Re: [PATCH] RISC-V: convert the mulh with 0 to mov 0 to the reg.
Oh. Yes. Thanks for Robin pointing this.
@yanzhang, could y
,
Yanzhang ; Robin Dapp ;
jeffreyalaw
Subject: Re: [PATCH] RISC-V: convert the mulh with 0 to mov 0 to the reg.
Good catch!
vmulh.vx v24,v24,zero -> vmv.v.i v1,0
can eliminate use of v24 and reduce register pressure.
But I wonder why you pick only VI_QHS?
+ [(set (match_operand:VI_QH
] RISC-V: convert the mulh with 0 to mov 0 to the reg.
Hi Yanzhang,
while I appreciate the optimization, I'm a bit wary about just adding a special
case for "0". Is that so common? Wouldn't we also like to have
* pow2_p (val) == << val and others?
* 1 should also be covered.
Regards
Robin
Hi Yanzhang,
while I appreciate the optimization, I'm a bit wary about just adding a special
case for "0". Is that so common? Wouldn't we also like to have
* pow2_p (val) == << val and others?
* 1 should also be covered.
Regards
Robin
he.zh...@rivai.ai
From: yanzhang.wang
Date: 2023-06-21 14:08
To: gcc-patches
CC: juzhe.zhong; kito.cheng; pan2.li; yanzhang.wang
Subject: [PATCH] RISC-V: convert the mulh with 0 to mov 0 to the reg.
From: Yanzhang Wang
This patch will optimize the below mulh example,
vint3
vai.ai
From: yanzhang.wang
Date: 2023-06-21 14:08
To: gcc-patches
CC: juzhe.zhong; kito.cheng; pan2.li; yanzhang.wang
Subject: [PATCH] RISC-V: convert the mulh with 0 to mov 0 to the reg.
From: Yanzhang Wang
This patch will optimize the below mulh example,
vint32m1_t shortcut_for_riscv_vmulh_case_0(
From: Yanzhang Wang
This patch will optimize the below mulh example,
vint32m1_t shortcut_for_riscv_vmulh_case_0(vint32m1_t v1, size_t vl) {
return __riscv_vmulh_vx_i32m1(v1, 0, vl);
}
from mulh pattern
vsetvli zero, a2, e32, m1, ta, ma
vmulh.vx v24, v24, zero
vs1r.vv24, 0(a0)
to belo
