Of cause, I'd like to make it generic. Thanks Robin’s advice! It's right, there're many similar situations.
But I'm not sure how to distinguish different operations. Currently, the VMULH is fixed as below. + (unspec:VI_QHS + [(vec_duplicate:VI_QHS + (match_operand:<VEL> 4 "reg_or_0_operand")) + (match_operand:VI_QHS 3 "register_operand")] VMULH) Do we need to define another UNSPEC ? And do we have any APIs to get the operation, like whether it's VMULH or POW ? Thanks, Yanzhang From: juzhe.zh...@rivai.ai <juzhe.zh...@rivai.ai> Sent: Wednesday, June 21, 2023 2:33 PM To: Robin Dapp <rdapp....@gmail.com>; Wang, Yanzhang <yanzhang.w...@intel.com>; gcc-patches <gcc-patches@gcc.gnu.org> Cc: Robin Dapp <rdapp....@gmail.com>; Kito.cheng <kito.ch...@sifive.com>; Li, Pan2 <pan2...@intel.com> Subject: Re: Re: [PATCH] RISC-V: convert the mulh with 0 to mov 0 to the reg. Oh. Yes. Thanks for Robin pointing this. @yanzhang, could you refine this patch more deeply to gain more optimizations ? Thanks. ________________________________ juzhe.zh...@rivai.ai<mailto:juzhe.zh...@rivai.ai> From: Robin Dapp<mailto:rdapp....@gmail.com> Date: 2023-06-21 14:27 To: yanzhang.wang<mailto:yanzhang.w...@intel.com>; gcc-patches<mailto:gcc-patches@gcc.gnu.org> CC: rdapp.gcc<mailto:rdapp....@gmail.com>; juzhe.zhong<mailto:juzhe.zh...@rivai.ai>; kito.cheng<mailto:kito.ch...@sifive.com>; pan2.li<mailto:pan2...@intel.com> Subject: Re: [PATCH] RISC-V: convert the mulh with 0 to mov 0 to the reg. Hi Yanzhang, while I appreciate the optimization, I'm a bit wary about just adding a special case for "0". Is that so common? Wouldn't we also like to have * pow2_p (val) == << val and others? * 1 should also be covered. Regards Robin
