zh...@rivai.ai; Wang, Yanzhang
>
> Subject: Re: [PATCH] RISC-V: Allow RVV VMS{Compare}(V1, V1) simplify to VMSET
>
> I will take V1 and commit to trunk after my local test is done :)
>
> On Fri, May 5, 2023 at 8:30 PM Li, Pan2 wrote:
> >
> > Hi kito,
> >
> >
Ok, sounds good. Thank you!
Pan
-Original Message-
From: Kito Cheng
Sent: Friday, May 5, 2023 8:37 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; Wang, Yanzhang
Subject: Re: [PATCH] RISC-V: Allow RVV VMS{Compare}(V1, V1) simplify to VMSET
I will take V1 and
From: Li, Pan2
> Sent: Wednesday, May 3, 2023 7:18 PM
> To: Jeff Law ; Kito Cheng
> Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; Wang, Yanzhang
> ; Andrew Waterman
> Subject: RE: [PATCH] RISC-V: Allow RVV VMS{Compare}(V1, V1) simplify to VMSET
>
> Thanks all for co
Subject: RE: [PATCH] RISC-V: Allow RVV VMS{Compare}(V1, V1) simplify to VMSET
Thanks all for comments, will work with kito to make it happen.
Pan
-Original Message-
From: Jeff Law
Sent: Wednesday, May 3, 2023 12:28 AM
To: Kito Cheng
Cc: Li, Pan2 ; gcc-patches@gcc.gnu.org;
juzhe.zh
: Allow RVV VMS{Compare}(V1, V1) simplify to VMSET
On 4/29/23 19:40, Kito Cheng wrote:
> Hi Jeff:
>
> The RTL pattern already models tail element and vector length well, so
> I don't feel the first version of Pan's patch has any problem?
>
> Input RTL pattern:
>
>
On 4/29/23 19:40, Kito Cheng wrote:
Hi Jeff:
The RTL pattern already models tail element and vector length well,
so I don't feel the first version of Pan's patch has any problem?
Input RTL pattern:
#(insn 10 7 12 2 (set (reg:VNx2BI 134 [ _1 ])
#(if_then_else:VNx2BI (unspec:VNx2BI [
policy and vector length as well.
Pan
-Original Message-
From: Kito Cheng
Sent: Sunday, April 30, 2023 9:40 AM
To: Jeff Law
Cc: Li, Pan2 ; gcc-patches@gcc.gnu.org;
juzhe.zh...@rivai.ai; Wang, Yanzhang ; Andrew Waterman
Subject: Re: [PATCH] RISC-V: Allow RVV VMS{Compare}(V1, V1) s
Hi Jeff:
The RTL pattern already models tail element and vector length well,
so I don't feel the first version of Pan's patch has any problem?
Input RTL pattern:
#(insn 10 7 12 2 (set (reg:VNx2BI 134 [ _1 ])
#(if_then_else:VNx2BI (unspec:VNx2BI [
#(const_vector:VNx2BI
On Sat, 29 Apr 2023 10:52:50 PDT (-0700), jeffreya...@gmail.com wrote:
On 4/29/23 11:48, Palmer Dabbelt wrote:
Yea. And taking advantage of that behavior is definitely a performance
issue for QEMU. There's still work to do though. QEMU on vector code
is running crazy slow.
I guess we're
On 4/29/23 11:48, Palmer Dabbelt wrote:
Yea. And taking advantage of that behavior is definitely a performance
issue for QEMU. There's still work to do though. QEMU on vector code
is running crazy slow.
I guess we're kind of off the rails for a GCC patch, but that's
definately true. Ac
On 4/29/23 11:21, Andrew Waterman wrote:
The relevant statement in the spec is that "the tail elements are always
updated with a tail-agnostic policy". The vmset.m instruction will
cause mask register bits [0, vl-1] to be set to 1; elements [vl,
VLMAX-1] will either be undisturbed or set
On Sat, 29 Apr 2023 10:46:37 PDT (-0700), jeffreya...@gmail.com wrote:
On 4/29/23 11:28, Palmer Dabbelt wrote:
On Sat, 29 Apr 2023 10:21:53 PDT (-0700), gcc-patches@gcc.gnu.org wrote:
On Sat, Apr 29, 2023 at 8:06 AM Jeff Law via Gcc-patches <
gcc-patches@gcc.gnu.org> wrote:
On 4/28/23 20:
On 4/29/23 11:28, Palmer Dabbelt wrote:
On Sat, 29 Apr 2023 10:21:53 PDT (-0700), gcc-patches@gcc.gnu.org wrote:
On Sat, Apr 29, 2023 at 8:06 AM Jeff Law via Gcc-patches <
gcc-patches@gcc.gnu.org> wrote:
On 4/28/23 20:55, Li, Pan2 wrote:
> Thanks Jeff for comments.
>
> It makes sense to m
On Sat, 29 Apr 2023 10:21:53 PDT (-0700), gcc-patches@gcc.gnu.org wrote:
On Sat, Apr 29, 2023 at 8:06 AM Jeff Law via Gcc-patches <
gcc-patches@gcc.gnu.org> wrote:
On 4/28/23 20:55, Li, Pan2 wrote:
> Thanks Jeff for comments.
>
> It makes sense to me. For the EQ operator we should have CONSTM
On Sat, Apr 29, 2023 at 8:06 AM Jeff Law via Gcc-patches <
gcc-patches@gcc.gnu.org> wrote:
>
>
>
> On 4/28/23 20:55, Li, Pan2 wrote:
> > Thanks Jeff for comments.
> >
> > It makes sense to me. For the EQ operator we should have CONSTM1.
> That's not the way I interpret the RVV documentation. Of co
On 4/28/23 20:55, Li, Pan2 wrote:
Thanks Jeff for comments.
It makes sense to me. For the EQ operator we should have CONSTM1.
That's not the way I interpret the RVV documentation. Of course it's
not terribly clear.I guess one could do some experiments with qemu
or try to dig into the
, 2023 10:55 AM
To: Jeff Law ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@sifive.com; Wang, Yanzhang
Subject: RE: [PATCH] RISC-V: Allow RVV VMS{Compare}(V1, V1) simplify to VMSET
Thanks Jeff for comments.
It makes sense to me. For the EQ operator we should have CONSTM1. Does this
-Original Message-
From: Jeff Law
Sent: Saturday, April 29, 2023 5:48 AM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@sifive.com; Wang, Yanzhang
Subject: Re: [PATCH] RISC-V: Allow RVV VMS{Compare}(V1, V1) simplify to VMSET
On 4/28/23 09:21, Pan Li via Gcc
On 4/28/23 09:21, Pan Li via Gcc-patches wrote:
From: Pan Li
When some RVV integer compare operators act on the same vector registers
without mask. They can be simplified to VMSET.
This PATCH allows the eq, le, leu, ge, geu to perform such kind of the
simplification by adding one macro in r
From: Pan Li
When some RVV integer compare operators act on the same vector registers
without mask. They can be simplified to VMSET.
This PATCH allows the eq, le, leu, ge, geu to perform such kind of the
simplification by adding one macro in riscv for simplify rtx.
Given we have:
vbool1_t test_
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