Re: [PATCH] [RISCV] Add Pattern for builtin overflow

2021-05-01 Thread Andrew Waterman
On Thu, Apr 29, 2021 at 3:02 PM Jim Wilson wrote: > > On Wed, Apr 28, 2021 at 4:04 PM Andrew Waterman wrote: >> >> > This is a good suggestion, but in the interests of making forward progress >> > here, I'd like to accept the patch and then file these as bugzillas as >> > ways to further improv

Re: [PATCH] [RISCV] Add Pattern for builtin overflow

2021-04-29 Thread Jim Wilson
On Wed, Apr 28, 2021 at 10:43 PM Levy Hsu wrote: > From: LevyHsu > > Added implementation for builtin overflow detection, new patterns are > listed below. > This looks OK. You are missing a ChangeLog entry. I added one. I had to fix some whitespace and formatting issues. Open parens should

Re: [PATCH] [RISCV] Add Pattern for builtin overflow

2021-04-29 Thread Jim Wilson
On Wed, Apr 28, 2021 at 4:04 PM Andrew Waterman wrote: > > This is a good suggestion, but in the interests of making forward > progress here, I'd like to accept the patch and then file these as > bugzillas as ways to further improve the patch. > > Agreed, these potential improvements are definite

[PATCH] [RISCV] Add Pattern for builtin overflow

2021-04-28 Thread Levy Hsu
From: LevyHsu Added implementation for builtin overflow detection, new patterns are listed below. --- Addition: signed addition (SImode in RV32 || DImode in RV64): add t0, t1, t2 sltit3, t2, 0 slt t

Re: [PATCH] [RISCV] Add Pattern for builtin overflow

2021-04-28 Thread Andrew Waterman
On Wed, Apr 28, 2021 at 1:18 PM Jim Wilson wrote: > > On Tue, Apr 27, 2021 at 12:45 AM Andrew Waterman wrote: >> >> > signed addition (SImode with RV64): >> > add t0, t1, t2 >> > sext.w t3, t0 >> > bne t0, t3, overflow >> >> The following version has the same instruction

Re: [PATCH] [RISCV] Add Pattern for builtin overflow

2021-04-28 Thread Jim Wilson
On Tue, Apr 27, 2021 at 12:45 AM Andrew Waterman wrote: > > signed addition (SImode with RV64): > > add t0, t1, t2 > > sext.w t3, t0 > > bne t0, t3, overflow > > The following version has the same instruction count but offers more ILP: > > add t0, t1, t2 > addw t3, t1

Re: [PATCH] [RISCV] Add Pattern for builtin overflow

2021-04-27 Thread Andrew Waterman
On Tue, Apr 27, 2021 at 12:18 AM Levy Hsu wrote: > > From: LevyHsu > > Added implementation for builtin overflow detection, new patterns are listed > below. > > --- > Addition: > > signed addition (SImode with RV32 || DImode with RV64):

[PATCH] [RISCV] Add Pattern for builtin overflow

2021-04-26 Thread Levy Hsu
From: LevyHsu Added implementation for builtin overflow detection, new patterns are listed below. --- Addition: signed addition (SImode with RV32 || DImode with RV64): add t0, t1, t2 sltit3, t2, 0 slt