On Wed, Apr 28, 2021 at 1:18 PM Jim Wilson <j...@sifive.com> wrote: > > On Tue, Apr 27, 2021 at 12:45 AM Andrew Waterman <and...@sifive.com> wrote: >> >> > signed addition (SImode with RV64): >> > add t0, t1, t2 >> > sext.w t3, t0 >> > bne t0, t3, overflow >> >> The following version has the same instruction count but offers more ILP: >> >> add t0, t1, t2 >> addw t3, t1, t2 >> bne t0, t3, overflow > > > This is a good suggestion, but in the interests of making forward progress > here, I'd like to accept the patch and then file these as bugzillas as ways > to further improve the patch.
Agreed, these potential improvements are definitely not blockers. >> >> > unsigned addition (SImode with RV64): >> > sext.w t3, t1 >> > addw t0, t1, t2 >> > bltu t0, t3, overflow >> >> I think you can do this in two instructions, similar to the previous pattern: >> >> addw t0, t1, t2 >> bltu t0, t1, overflow > > > Likewise. >> >> > signed subtraction (SImode with RV64): >> > sub t0, t1, t2 >> > sext.w t3, t0 >> > bne t0, t3, overflow >> >> See analogous addition comment. > > > Likewise. >> >> >> > unsigned subtraction (SImode with RV64): >> > sext.w t3, t1 >> > subw t0, t1, t2 >> > bltu t0, t3, overflow >> >> See analogous addition comment. > > > Likewise. >> >> > unsigned multiplication (SImode with RV64): >> > slli t0,t0,32 >> > slli t1,t1,32 >> > srli t0,t0,32 >> > srli t1,t1,32 >> > mul t0,t0,t1 >> > srai t5,t0,32 >> > bne t5, 0, overflow >> >> I think you can eliminate the first two right shifts by replacing mul >> with mulhu... something like: >> >> slli rx, rx, 32 >> slli ry, ry, 32 >> mulhu rz, rx, ry >> srli rt, rz, 32 >> bnez rt, overflow > > > Likewise, except this should be a separate bugzilla. > > Jim
