Re: [PATCH][AArch64] Fix PR/65770 vstN_lane on bigendian

2015-04-29 Thread Marcus Shawcroft
On 16 April 2015 at 18:27, Alan Lawrence wrote: > As per bugzilla entry, indices in the generated assembly for bigendian are > flipped when they should not be (and, flipped always relative to a > Q-register!). > > This flips the lane indices back again at assembly time, fixing PR. The > "indices"

Re: [PATCH][AArch64] Fix PR/65770 vstN_lane on bigendian

2015-04-29 Thread Alan Lawrence
Alan Lawrence wrote: As per bugzilla entry, indices in the generated assembly for bigendian are flipped when they should not be (and, flipped always relative to a Q-register!). This flips the lane indices back again at assembly time, fixing PR. The "indices" contained in the RTL are still wron

[PATCH][AArch64] Fix PR/65770 vstN_lane on bigendian

2015-04-16 Thread Alan Lawrence
As per bugzilla entry, indices in the generated assembly for bigendian are flipped when they should not be (and, flipped always relative to a Q-register!). This flips the lane indices back again at assembly time, fixing PR. The "indices" contained in the RTL are still wrong for D registers, but