Alan Lawrence wrote:
As per bugzilla entry, indices in the generated assembly for bigendian are
flipped when they should not be (and, flipped always relative to a Q-register!).
This flips the lane indices back again at assembly time, fixing PR. The
"indices" contained in the RTL are still wrong for D registers, but these are
only parameters to an UNSPEC and so never acted upon. (Nonetheless I intend to
fix this anomaly in later patches).
Tested check-gcc on aarch64-none-elf and aarch64_be-none-elf.
New test (initially failing on bigendian) now passing on both.
gcc/ChangeLog:
PR target/65770
config/aarch64/aarch64-simd.md (vec_store_lanesoi_lane<mode>,
vec_store_lanesci_lane<mode>, vec_store_lanesxi_lane<mode>):
Flip lane index back at assembly time for bigendian.
gcc/testsuite/ChangeLog:
PR target/65770
gcc.target/aarch64/vstN_lane_1.c: New file.
Ping.
