Re: [PATCH], PR target/93569, Fix PowerPC vsx-builtin-15d.c test case

2020-02-06 Thread Michael Meissner
On Thu, Feb 06, 2020 at 09:49:18AM -0600, Segher Boessenkool wrote: > Hi! > > On Thu, Feb 06, 2020 at 08:29:41AM -0500, Michael Meissner wrote: > > --- /tmp/eAu61F_rs6000.c2020-02-05 18:08:48.698992017 -0500 > > +++ gcc/config/rs6000/rs6000.c 2020-02-05 17:23:55.733650185 -0500 > > @@ -24

Re: [PATCH], PR target/93569, Fix PowerPC vsx-builtin-15d.c test case

2020-02-06 Thread Segher Boessenkool
Hi! On Thu, Feb 06, 2020 at 08:29:41AM -0500, Michael Meissner wrote: > --- /tmp/eAu61F_rs6000.c 2020-02-05 18:08:48.698992017 -0500 > +++ gcc/config/rs6000/rs6000.c2020-02-05 17:23:55.733650185 -0500 > @@ -24943,9 +24943,13 @@ reg_to_non_prefixed (rtx reg, machine_mo > } > >

[PATCH], PR target/93569, Fix PowerPC vsx-builtin-15d.c test case

2020-02-06 Thread Michael Meissner
When I applied my previous patches for vec_extract, I switched to using reg_to_non_prefixed to validate the vector extract address. It uncovered a bug that reg_to_non_prefixed allowed D-FORM (reg+offset) addresses to load up Altivec registers on power7 and power8. However, those systems only supp