Hi!
On Thu, Feb 06, 2020 at 08:29:41AM -0500, Michael Meissner wrote:
> --- /tmp/eAu61F_rs6000.c 2020-02-05 18:08:48.698992017 -0500
> +++ gcc/config/rs6000/rs6000.c 2020-02-05 17:23:55.733650185 -0500
> @@ -24943,9 +24943,13 @@ reg_to_non_prefixed (rtx reg, machine_mo
> }
>
> /* Altivec registers use DS-mode for scalars, and DQ-mode for vectors, IEEE
> - 128-bit floating point, and 128-bit integers. */
> + 128-bit floating point, and 128-bit integers. Before power9, only
> indexed
> + addressing was available. */
> else if (ALTIVEC_REGNO_P (r))
> {
> + if (!TARGET_P9_VECTOR)
> + return NON_PREFIXED_X;
> +
> if (mode == SFmode || size == 8 || FLOAT128_2REG_P (mode))
> return NON_PREFIXED_DS;
That looks fine, but is this complete? What about the other VSRs? Like
right before this:
if (FP_REGNO_P (r))
{
if (mode == SFmode || size == 8 || FLOAT128_2REG_P (mode))
return NON_PREFIXED_D;
else if (size < 8)
return NON_PREFIXED_X;
else if (TARGET_VSX && size >= 16
&& (VECTOR_MODE_P (mode)
|| FLOAT128_VECTOR_P (mode)
|| mode == TImode || mode == CTImode))
return NON_PREFIXED_DQ;
else
return NON_PREFIXED_DEFAULT;
}
If we are dealing with a SF or DF (or whatever else in a "legacy" FPR),
that is fine, but what about vectors in those regs? It says we can use
DQ-mode here, but that is only true from p9 onward, no?
Segher
