Re: [PATCH,rs6000] Make MMA builtins use opaque modes [v2]

2020-11-20 Thread Segher Boessenkool
Hi! As Peter remarked, the input_operand's in the disassemble patterns are better as something more specific (input_operand has everything a "mov" pattern can handle, but pretty much nothing else can on a load/store architecture like Power -- it will likely still work, but only after reloads, so n

[PATCH,rs6000] Make MMA builtins use opaque modes [v2]

2020-11-19 Thread acsawdey--- via Gcc-patches
From: Aaron Sawdey Segher & Bergner - Thanks for the reviews, here's the updated patch after fixing those things. We now have an UNSPEC for xxsetaccz, and an accompanying change to rs6000_rtx_costs to make it be cost 0 so that CSE doesn't try to replace it with a bunch of register moves. If bo

[PATCH,rs6000] Make MMA builtins use opaque modes [v2]

2020-11-19 Thread Aaron Sawdey via Gcc-patches
For some reason this patch never showed up on gcc-patches. Aaron Sawdey, Ph.D. saw...@linux.ibm.com IBM Linux on POWER Toolchain > Begin forwarded message: > > From: acsaw...@linux.ibm.com > Subject: [PATCH,rs6000] Make MMA builtins use opaque modes [v2] > Date: November 19, 2

Re: [PATCH,rs6000] Make MMA builtins use opaque modes [v2]

2020-11-19 Thread Peter Bergner via Gcc-patches
On 11/19/20 12:58 PM, acsaw...@linux.ibm.com wrote: > +(define_expand "mma_disassemble_pair" > + [(match_operand:V16QI 0 "mma_disassemble_output_operand") > + (match_operand:OO 1 "input_operand") > + (match_operand 2 "const_0_to_1_operand")] Maybe we should use vsx_register_operand instead of

Re: [PATCH,rs6000] Make MMA builtins use opaque modes

2020-11-17 Thread Peter Bergner via Gcc-patches
On 11/17/20 5:01 PM, Segher Boessenkool wrote: > On Tue, Nov 17, 2020 at 12:41:58PM -0600, Peter Bergner wrote: >>> +;; Return 1 if this operand is valid for an MMA disassemble insn. >>> +(define_predicate "mma_disassemble_output_operand" >>> + (match_code "reg,subreg,mem") >>> +{ >>> + if (REG_P

Re: [PATCH,rs6000] Make MMA builtins use opaque modes

2020-11-17 Thread Segher Boessenkool
On Tue, Nov 17, 2020 at 12:41:58PM -0600, Peter Bergner wrote: > > +;; Return 1 if this operand is valid for an MMA disassemble insn. > > +(define_predicate "mma_disassemble_output_operand" > > + (match_code "reg,subreg,mem") > > +{ > > + if (REG_P (op) && !vsx_register_operand (op, mode)) > > +

Re: [PATCH,rs6000] Make MMA builtins use opaque modes

2020-11-17 Thread Segher Boessenkool
Hi! On Tue, Nov 17, 2020 at 11:48:04AM -0600, acsaw...@linux.ibm.com wrote: > This patch changes powerpc MMA builtins to use the new opaque > mode class and use modes OO (32 bytes) and XO (64 bytes) > instead of POI/PXI. Using the opaque modes prevents > optimization from trying to do anything wit

Re: [PATCH,rs6000] Make MMA builtins use opaque modes

2020-11-17 Thread Peter Bergner via Gcc-patches
On 11/17/20 11:48 AM, acsaw...@linux.ibm.com wrote: > -;; The MMA patterns use the multi-register PXImode and POImode partial > +;; The MMA patterns use the multi-register XOmode and OOmode partial > ;; integer modes to implement the target specific __vector_quad and XOmode and OOmode are not par

[PATCH,rs6000] Make MMA builtins use opaque modes

2020-11-17 Thread acsawdey--- via Gcc-patches
From: Aaron Sawdey This patch changes powerpc MMA builtins to use the new opaque mode class and use modes OO (32 bytes) and XO (64 bytes) instead of POI/PXI. Using the opaque modes prevents optimization from trying to do anything with vector pair/quad, which was the problem we were seeing with th