On Tue, Nov 17, 2020 at 12:41:58PM -0600, Peter Bergner wrote:
> > +;; Return 1 if this operand is valid for an MMA disassemble insn.
> > +(define_predicate "mma_disassemble_output_operand"
> > + (match_code "reg,subreg,mem")
> > +{
> > + if (REG_P (op) && !vsx_register_operand (op, mode))
> > + return false;
> > + return true;
> > +})
>
> Do we really want to accept subregs here? If so, why are they not also
> required
> to be vsx_register_operand()?
That *does* allow subregs!
;; Return 1 if op is a VSX register.
(define_predicate "vsx_register_operand"
(match_operand 0 "register_operand")
{
if (SUBREG_P (op))
{
if (TARGET_NO_SF_SUBREG && sf_subreg_operand (op, mode))
return 0;
op = SUBREG_REG (op);
}
...
int
register_operand (rtx op, machine_mode mode)
{
if (GET_CODE (op) == SUBREG)
{
rtx sub = SUBREG_REG (op);
/* Before reload, we can allow (SUBREG (MEM...)) as a register operand
because it is guaranteed to be reloaded into one.
Just make sure the MEM is valid in itself.
(Ideally, (SUBREG (MEM)...) should not exist after reload,
but currently it does result from (SUBREG (REG)...) where the
reg went on the stack.) */
if (!REG_P (sub) && (reload_completed || !MEM_P (sub)))
return 0;
}
else if (!REG_P (op))
return 0;
return general_operand (op, mode);
}
(The SFmode thing and subregs-of-mem are complifying things, just to
keep things interesting.)
We need to allow subregs of reg pretty much always, for reinterpret_cast
like things (say, changing one vector mode to another).
Segher
