回复：[PATCH 0/4] RISC-V: Add new segment load/store intrinsics for xtheadvector

Hello! Actually the T-head segment load/store instructions and intrinsics is different from standard vector instruction and intrinsics. In doc https://github.com/XUANTIE-RV/thead-extension-spec/edit/master/xtheadvector/intrinsics.adoc

回复：[PATCH] [RFC] RISC-V: Add extra check to help choosing multilib with equivalent arch.

> But rv32imaf_zca means we don't have zcf, so it can not select > rv32imac, otherwise that means the final binary will have zcf > instruction and that won't be able to run on env that only have > rv32imaf_zca. In my opinion the arch of multilib is the arch used when compiling the lib, that is the

[PATCH 2/4] RISC-V: Add support for xtheadvector strided segment load/store intrinsics

From: Yunze Zhu This commit add support for xtheadvector-specific strided segment load/store intrinsics with b/h/w suffix. We also defined enum to be used in thead-vector-builtins-bases.cc https://github.com/XUANTIE-RV/thead-extension-spec/pull/66 gcc/ChangeLog: * config/riscv/riscv-vec

[PATCH 1/4] RISC-V: Add support for xtheadvector unit-stride segment load/store intrinsics

From: Yunze Zhu This commit add support for xtheadvector-specific unit-stride segment load/store intrinsics with b/h/w suffix. We also defined enum to be used in thead-vector-builtins-bases.cc https://github.com/XUANTIE-RV/thead-extension-spec/pull/66 gcc/ChangeLog: * config.gcc: Add ne

[PATCH 3/4] RISC-V: Add support for xtheadvector indexed segment load/store intrinsics

From: Yunze Zhu This commit add support for xtheadvector-specific indexed segment load/store intrinsics with b/h/w suffix. We also defined enum to be used in thead-vector-builtins-bases.cc https://github.com/XUANTIE-RV/thead-extension-spec/pull/66 gcc/ChangeLog: * config/riscv/riscv-vec

[PATCH 0/4] RISC-V: Add new segment load/store intrinsics for xtheadvector

From: Yunze Zhu This series add xtheadvector-specific segment load/store intrinsics support, including: [1/4] xtheadvector unit stride segment load/store intrinsics, [2/4] xtheadvector stride segment load/store intrinsics, [3/4] xtheadvector indexed stride segment load/store intrinsics, [4/4] xt

[PATCH 4/4] RISC-V: Add support for xtheadvector fault-only-first segment load/store intrinsics

From: Yunze Zhu This commit add support for xtheadvector-specific fault-only-first segment load/store intrinsics with b/h/w suffix. We also defined enum to be used in thead-vector-builtins-bases.cc https://github.com/XUANTIE-RV/thead-extension-spec/pull/66 gcc/ChangeLog: * config/riscv/

回复：[PATCH] [RFC] RISC-V: Add extra check to help choosing multilib with equivalent arch.

ch must contain zcf, because C+F is equivalent to F+Zca+Zcf and vice versa. The arch rv32imaf_zca contains F and zca but no zcf so we cannot imply C and therefore multilb rv32imac/mabi=ilp32 cannot be selected. -- 发件人：Kito Cheng 发送时间：2

[PATCH] [RFC] RISC-V: Add extra check to help choosing multilib with equivalent arch.

From: Yunze Zhu Currently when choosing multilib set for target like march=rv32imaf_zca/mabi=ilp32, gnu toolchain reports "Cannot find suitable multilib set". This is because in current dependent extension zca implies c when has combinations of extensions: Zca, F_Zca_Zcf or FD_Zca_Zcf_Zcd, and

[RFC PATCH v2] RISC-V:Fix th.vsetvli generates from vext_x_v with wrong operand

From: Yunze Zhu Fix a bug th.vsetvli generates from vext_x_v with an imm operand, which reports illegal operand. This patch fix this by replacing imm operand with reg operand in th.vsetvli. gcc/ChangeLog: * config/riscv/riscv-vsetvl.cc: gcc/testsuite/ChangeLog: * gcc.target/ri

[PATCH] RISC-V:Fix th.vsetvli generates from vext_x_v with wrong operand

From: Yunze Zhu Fix a bug th.vsetvli generates from vext_x_v with an imm operand, which reports illegal operand. This patch fix this by replacing imm operand with reg operand in th.vsetvli. gcc/ChangeLog: * config/riscv/riscv-vsetvl.cc: gcc/testsuite/ChangeLog: * gcc.target/ri