Hello!
Actually the T-head segment load/store instructions and intrinsics is different
from standard vector instruction and intrinsics.
In doc
https://github.com/XUANTIE-RV/thead-extension-spec/edit/master/xtheadvector/intrinsics.adoc
<https://github.com/XUANTIE-RV/thead-extension-spec/edit/master/xtheadvector/intrinsics.adoc
>
we listed intrinsic list, and from which I shall take intrinsic:
vint16m1x2_t __riscv_th_vlseg2b_v_i16m1x2 (const int16_t *a, size_t vl);
as example.
This intrinsic means unit-strided loading 2 8-bit data and extend them into 2
16bit data,
while standard segments load/store do not do extend.
In standard segments load pattern pred_unit_strided_load we can only get info
like sew from mode,
but we cannot pass target data length to extend with mode in T-head segment
load/store.
Since we are using unspec to pass target data length, we cannot reusing
standard vector instruction
pattens without making change to inputs of the patterns, and that is why we
choose to add new patterns
rather than reuse standard ones.
> Hi Yunze:
>
> I thought the T-head vector should just reuse segments load/store
> pattern from standard vector instruction is enough and then adjust the
> output name at th_asm_output_opcode , do you have a good reason why we
> need to add those patterns for T-head vector again? I am really
> concerned about this patch set increasing the number of patterns too
> much.
