Ping!!
From: Gcc-patches
on behalf of
Srinath Parvathaneni via Gcc-patches
Sent: 27 January 2023 17:44
To: gcc-patches@gcc.gnu.org
Cc: nd ; Richard Earnshaw ; Kyrylo
Tkachov
Subject: [PATCH][GCC] arm: Optimize arm-mlib.h header inclusion (pr108505).
Hello
Hello,
I have committed a fix [1] into gcc trunk for a build issue mentioned in
pr108505 and
latter received few upstream comments proposing more robust fix for this issue.
In this patch I'm addressing those comments and sending this as a followup
patch.
Regression tested on arm-none-eabi targ
Hello,
The patch fixes the build issue for arm-none-eabi target configured with
--with-multilib-list=aprofile,rmprofile, in which case the header file
arm/arm-mlib.h is being included more than once and the toolchain build
is failing (PR108505).
Regression tested on arm-none-eabi target and found
Hello,
This patch fixes the documentation for -mbranch-protection command line option.
Committed this patch to trunk as obvious fix.
Regards,
Srinath.
gcc/ChangeLog:
2023-01-23 Srinath Parvathaneni
* doc/invoke.texi (-mbranch-protection): Update documentation.
###
Hi,
This patch adds support for Arm frame unwinding instruction "0xb5" [1]. When
an exception is taken and "0xb5" instruction is encounter during runtime
stack-unwinding, we use effective vsp as modifier in pointer authentication.
On completion of stack unwinding if "0xb5" instruction is not encou
> To: Srinath Parvathaneni
> > > Cc: gcc-patches@gcc.gnu.org; Richard Earnshaw
> > > ; Kyrylo Tkachov
>
> > > Subject: Re: [PATCH][GCC] arm: Add support for new frame unwinding
> > > instruction "0xb5".
> > >
> > > On
Hello,
This patch teaches the DWARF support in gcc about RA_AUTH_CODE pseudo
hard-register and also
updates the ".save", ".cfi_register", ".cfi_offset", ".cfi_restore" directives
accordingly.
This patch also adds support to emit ".pacspval" directive when "pac ip, lr,
sp" instruction
in genera
Hi,
This patch adds the support for pacbti multlilib linking by making
"-mbranch-protection=none" as default multilib option for arm-none-eabi
target.
Eg 1.
If the passed command line flags are (without mbranch-protection):
a) -march=armv8.1-m.main+mve -mfloat-abi=hard -mfpu=auto
"-mbranch-prot
Hello,
This patch teaches the DWARF support in gcc about RA_AUTH_CODE pseudo
hard-register and also
updates the ".save", ".cfi_register", ".cfi_offset", ".cfi_restore" directives
accordingly.
This patch also adds support to emit ".pacspval" directive when "pac ip, lr,
sp" instruction
in genera
Hi,
This patch adds cde feature (optional) support for Cortex-M55 CPU, please refer
[1] for more details. To use this feature we need to specify +cdecpN
(e.g. -mcpu=cortex-m55+cdecp), where N is the coprocessor number 0 to 7.
Bootstrapped for arm-none-linux-gnueabihf target, regression tested
on
> Cc: Richard Earnshaw <mailto:richard.earns...@arm.com>
> Subject: Re: [GCC][PATCH] arm: Add cde feature support for Cortex-M55
> CPU.
>
> Hi Srinath,
>
>
> On 10/10/22 10:20, Srinath Parvathaneni via Gcc-patches wrote:
> > Hi,
> >
> > This patch adds
Ping!!
From: Gcc-patches
on behalf of
Srinath Parvathaneni via Gcc-patches
Sent: 09 November 2022 14:32
To: gcc-patches@gcc.gnu.org
Cc: Richard Earnshaw ; Kyrylo Tkachov
Subject: [GCC][PATCH 13/15, v4] arm: Add support for dwarf debug directives and
pseudo
stophe Lyon
> Sent: Monday, October 17, 2022 2:30 PM
> To: Srinath Parvathaneni ; gcc-
> patc...@gcc.gnu.org
> Cc: Richard Earnshaw
> Subject: Re: [GCC][PATCH] arm: Add cde feature support for Cortex-M55
> CPU.
>
> Hi Srinath,
>
>
> On 10/10/22 10:20, Srinath Par
Ping!!
From: Gcc-patches
on behalf of
Srinath Parvathaneni via Gcc-patches
Sent: 31 October 2022 15:36
To: gcc-patches@gcc.gnu.org
Cc: Richard Earnshaw
Subject: [GCC][PATCH v2] arm: Add pacbti related multilib support for
armv8.1-m.main.
Hi,
This patch
g
> instruction "0xb5".
>
> On Thu, Nov 10, 2022 at 10:38 AM Srinath Parvathaneni via Gcc-patches patc...@gcc.gnu.org> wrote:
> >
> > Hi,
> >
> > This patch adds support for Arm frame unwinding instruction "0xb5"
> > [1]. When an exception
Hi,
> -Original Message-
> From: Kyrylo Tkachov
> Sent: Monday, November 14, 2022 2:47 PM
> To: Srinath Parvathaneni ; gcc-
> patc...@gcc.gnu.org
> Cc: Richard Sandiford
> Subject: RE: [PATCH][GCC] aarch64: Add support for Cortex-X3 CPU.
>
>
>
> > -Original Message-
> > From:
Hi,
This patch adds support for Cortex-X3 CPU.
Bootstrapped on aarch64-none-linux-gnu and found no regressions.
Ok for GCC master?
Regards,
Srinath.
gcc/ChangeLog:
2022-11-09 Srinath Parvathaneni
* config/aarch64/aarch64-cores.def (AARCH64_CORE): Add Cortex-X3 CPU.
* c
Hi,
> -Original Message-
> From: Kyrylo Tkachov
> Sent: Friday, November 11, 2022 2:24 PM
> To: Srinath Parvathaneni ; gcc-
> patc...@gcc.gnu.org
> Cc: Richard Sandiford
> Subject: RE: [PATCH][GCC] aarch64: Add support for Cortex-A715 CPU.
>
> Hi Srinath,
>
> > -Original Message---
Hi,
This patch adds support for Cortex-X1C CPU.
Bootstrapped on aarch64-none-linux-gnu and found no regressions.
Ok for GCC master?
Regards,
Srinath.
gcc/ChangeLog:
2022-11-09 Srinath Parvathaneni
* config/aarch64/aarch64-cores.def (AARCH64_CORE): Add Cortex-X1C CPU.
*
Hi,
This patch adds support for Cortex-A715 CPU.
Bootstrapped on aarch64-none-linux-gnu and found no regressions.
Ok for GCC master?
Regards,
Srinath.
gcc/ChangeLog:
2022-11-09 Srinath Parvathaneni
* config/aarch64/aarch64-cores.def (AARCH64_CORE): Add Cortex-A715 CPU.
Hi,
This patch adds support for Arm frame unwinding instruction "0xb5" [1]. When
an exception is taken and "0xb5" instruction is encounter during runtime
stack-unwinding, we use effective vsp as modifier in pointer authentication.
On completion of stack unwinding if "0xb5" instruction is not encou
Hi,
This patch adds the -mcpu support for the Arm Cortex-X1C CPU.
Regression tested on arm-none-eabi and bootstrapped on arm-none-linux-gnueabihf.
Ok for GCC master?
Regards,
Srinath.
gcc/ChangeLog:
2022-11-09 Srinath Parvathaneni
* config/arm/arm-cpus.in (c
Hello,
This patch teaches the DWARF support in gcc about RA_AUTH_CODE pseudo
hard-register and also
updates the ".save", ".cfi_register", ".cfi_offset", ".cfi_restore" directives
accordingly.
This patch also adds support to emit ".pacspval" directive when "pac ip, lr,
sp" instruction
in genera
Hi,
This patch adds the support for pacbti multlilib linking by making
"-mbranch-protection=none" as default in the command line for all M-profile
targets and uses "-mbranch-protection=none" for multilib matching. If any
valid value is passed to "-mbranch-protection" in the command line, this
new
rinath,
>
>
> On 10/10/22 10:20, Srinath Parvathaneni via Gcc-patches wrote:
> > Hi,
> >
> > This patch adds cde feature (optional) support for Cortex-M55 CPU,
> > please refer [1] for more details. To use this feature we need to
> > specify +cdecpN (e.g
Hi,
This patch adds cde feature (optional) support for Cortex-M55 CPU, please refer
[1] for more details. To use this feature we need to specify +cdecpN
(e.g. -mcpu=cortex-m55+cdecp), where N is the coprocessor number 0 to 7.
Bootstrapped for arm-none-linux-gnueabihf target, regression tested
on
Hello,
This patch teaches the DWARF support in gcc about RA_AUTH_CODE pseudo
hard-register and also
.save {ra_auth_code} and .cfi_offset ra_auth_code dwarf directives for
the PAC feature
in Armv8.1-M architecture.
RA_AUTH_CODE register number is 107 and it's dwarf register number is 143.
Whe
Hi,
This patch adds the -mcpu support for the Arm Cortex-M85 CPU which is an
Armv8.1-M Mainline CPU supporting MVE and PACBTI by default.
-mpcu=cortex-m85 switch by default matches to
-march=armv8.1-m.main+pacbti+mve.fp+fp.dp.
Also following options are provided to disable default features.
+no
Hi,
This patch supports following -march/-mbranch-protection combination by linking
them
to existing pacbti multilibs.
$ -march=armv8.1-m.main+pacbti+fp.dp+mve.fp -mbranch-protection=standard
-mfloat-abi=hard -mthumb
$ -march=armv8.1-m.main+pacbti+fp.dp+mve -mbranch-protection=standard
-mfloa
Hi,
This patch documents the following options for Arm Cortex-M55 CPU under -mcpu=
list.
+nomve.fp (disables MVE single precision floating point instructions)
+nomve (disables MVE integer and single precision floating point instructions)
+nodsp (disables dsp, MVE integer and single precision flo
Hi,
This patch adds the -mcpu support for the Arm Cortex-M85 CPU which is an
Armv8.1-M Mainline CPU supporting MVE and PACBTI by default.
-mpcu=cortex-m85 switch by default matches to
-march=armv8.1-m.main+pacbti+mve.fp+fp.dp.
Also following options are provided to disable default features.
+no
Ping!!
> -Original Message-
> From: Gcc-patches bounces+srinath.parvathaneni=arm@gcc.gnu.org> On Behalf Of Srinath
> Parvathaneni via Gcc-patches
> Sent: 05 May 2022 12:02
> To: gcc-patches@gcc.gnu.org
> Cc: Richard Earnshaw
> Subject: [PATCH v2][GCC] ar
Hello,
This patch teaches the DWARF support in gcc about RA_AUTH_CODE pseudo
hard-register and also
.save {ra_auth_code} and .cfi_offset ra_auth_code dwarf directives for
the PAC feature
in Armv8.1-M architecture.
RA_AUTH_CODE register number is 107 and it's dwarf register number is 143.
Whe
Ping!!
From: Srinath Parvathaneni
Sent: 13 December 2021 10:44
To: gcc-patches@gcc.gnu.org
Cc: Kyrylo Tkachov ; Richard Earnshaw
; Tejas Belagod
Subject: Re: [PATCH v2][GCC] arm: Add support for dwarf debug directives and
pseudo hard-register for PAC feature.
Ping!!
From: Srinath Parvathaneni
Sent: 12 November 2021 18:03
To: gcc-patches@gcc.gnu.org
Cc: Kyrylo Tkachov ; Richard Earnshaw
; Tejas Belagod
Subject: [PATCH v2][GCC] arm: Add support for dwarf debug directives and pseudo
hard-register for PAC feature.
Hello
Hello,
This patch teaches the DWARF support in gcc about RA_AUTH_CODE pseudo
hard-register and also
.save {ra_auth_code} and .cfi_offset ra_auth_code dwarf directives for
the PAC feature
in Armv8.1-M architecture.
RA_AUTH_CODE register number is 107 and it's dwarf register number is 143.
Whe
Hello,
This patch teaches the DWARF support in gcc about RA_AUTH_CODE pseudo
hard-register and also
.save {ra_auth_code} and .cfi_offset ra_auth_code dwarf directives for
the PAC feature
in Armv8.1-M architecture.
RA_AUTH_CODE register number is 107 and it's dwarf register number is 143.
Whe
Hi,
This is a backport to gcc-11 and the patch applied cleanly on the branch.
On passing +cdecp[0-7] extension to the -march string in command line options,
multilib linking is failing as mentioned in PR100856. This patch fixes this
issue by
generating a separate canonical string by removing com
Hi,
This is a backport to gcc-10 and the patch applied cleanly on the branch.
On passing +cdecp[0-7] extension to the -march string in command line options,
multilib linking is failing as mentioned in PR100856. This patch fixes this
issue by
generating a separate canonical string by removing com
Hi Richard,
I have all addressed all your review comments (in [1]) in the below patch.
On passing +cdecp[0-7] extension to the -march string in command line options,
multilib linking is failing as mentioned in PR100856. This patch fixes this
issue by
generating a separate canonical string by rem
Hi,
This patch fixes the issue mentioned in PR101016, which is mve polymorphic
variants
failing at linking with undefined reference to "__ARM_undef" error.
Regression tested on arm-none-eabi and found no regressions.
This patch have cleanly applied, ok for the GCC-10 branch?
Regards,
Srinath.
Hi,
This patch fixes the issue mentioned in PR101016, which is mve polymorphic
variants
failing at linking with undefined reference to "__ARM_undef" error.
Regression tested on arm-none-eabi and found no regressions.
This patch have cleanly applied, ok for the GCC-11 branch?
gcc/ChangeLog:
20
Hi,
The current CMSE support in the multilib build for
"-march=armv8.1-m.main+mve -mfloat-abi=hard -mfpu=auto" is broken
as specified in PR99939 and this patch fixes the issue.
Regression tested on arm-none-eabi and found no regressions.
This patch have cleanly applied, ok for the GCC-10 branch?
Hi,
The current CMSE support in the multilib build for
"-march=armv8.1-m.main+mve -mfloat-abi=hard -mfpu=auto" is broken
as specified in PR99939 and this patch fixes the issue.
Regression tested on arm-none-eabi and found no regressions.
This patch have cleanly applied, ok for the GCC-11 branch?
Hi Richard,
I have addressed all your review comments in
https://gcc.gnu.org/pipermail/gcc-patches/2021-June/571739.html
in the following patch.
The current CMSE support in the multilib build for "-march=armv8.1-m.main+mve
-mfloat-abi=hard -mfpu=auto"
is broken as specified in PR99939 and this
Hi Richard,
I have addressed all your review comments in
https://gcc.gnu.org/pipermail/gcc-patches/2021-June/571739.html
in the following patch.
The current CMSE support in the multilib build for "-march=armv8.1-m.main+mve
-mfloat-abi=hard -mfpu=auto"
is broken as specified in PR99939 and this
gcc-
> patc...@gcc.gnu.org
> Cc: Richard Earnshaw
> Subject: Re: [GCC][PATCH] arm: Fix multilib mapping for CDE extensions.
>
>
>
> On 01/06/2021 18:08, Srinath Parvathaneni via Gcc-patches wrote:
> > Hi All,
> >
> > On passing +cdecp[0-7] extension to the
Hi,
This patch fixes the issue mentioned in PR101016, which is mve polymorphic
variants
failing at linking with undefined reference to "__ARM_undef" error.
Regression tested on arm-none-eabi and found no regressions.
Ok for master?
Regards,
Srinath.
gcc/ChangeLog:
2021-06-10 Srinath Parvath
;
>
>
> On 12/04/2021 14:04, Srinath Parvathaneni via Gcc-patches wrote:
> > Hi,
> >
> > The current CMSE support in the multilib build for "-march=armv8.1-
> m.main+mve -mfloat-abi=hard -mfpu=auto"
> > is broken as specified in PR99939 and this patch
Hi All,
On passing +cdecp[0-7] extension to the -march string in command line options,
multilib linking is failing as mentioned in PR100856. This patch fixes this
issue by generating a separate -march string only for multilib comparison.
Regression tested on arm-none-eabi and found no regressions
Ping!!
> -Original Message-
> From: Srinath Parvathaneni
> Sent: 30 April 2021 16:24
> To: gcc-patches@gcc.gnu.org
> Cc: Kyrylo Tkachov ; Richard Earnshaw
>
> Subject: [GCC-10 backport][PATCH] arm: _Generic feature failing with ICE for
> -O0 (pr97205).
>
> Hi,
>
> This is a backport to
Hi,
This is a backport to GCC-10 branch, this patch got applied cleanly on the
branch.
This patch removes several duplicated intrinsic definitions from
arm_mve.h mentioned in PR100419 and also fixes the wrong arguments
in few of intrinsics polymorphic variants.
Ok for GCC-10 branch?
gcc/Change
Hi,
This is a backport to GCC-11 branch, this patch got applied cleanly on the
branch.
This patch removes several duplicated intrinsic definitions from
arm_mve.h mentioned in PR100419 and also fixes the wrong arguments
in few of intrinsics polymorphic variants.
Ok for GCC-11 branch?
gcc/Change
Hi,
This is a backport to gcc-10, cleanly applied on the branch.
As reported in bugzilla when the -mcmse option is used while compiling for size
(-Os) with a thumb-1 target the generated code will clear the registers r7-r10.
These however are callee saved and should be preserved accross ABI bound
Hi,
This is a backport to gcc-10, cleanly applied on the branch.
This patch changes the test to use the effective-target machinery disables the
error message "ARMv8-M Security Extensions incompatible with selected FPU" when
-mfloat-abi=soft.
Further changes 'asm' to '__asm__' to avoid failures wi
>
>
> On 05/05/2021 10:56, Srinath Parvathaneni via Gcc-patches wrote:
> > Hi All,
> >
> > This patch removes several duplicated intrinsic definitions from
> > arm_mve.h mentioned in PR100419 and also fixes the wrong arguments
> > in few of intrinsics p
Hi All,
This patch removes several duplicated intrinsic definitions from
arm_mve.h mentioned in PR100419 and also fixes the wrong arguments
in few of intrinsics polymorphic variants.
Regression tested and found no issues.
Ok for master ? GCC-11 and GCC-10 branch backports?
gcc/ChangeLog:
2021-0
Hi,
This is a backport to GCC-10 to fix PR97205, patch applies
cleanly on the branch.
Regression tested and found no issues.
Ok for GCC-10 backport?
Regards,
Srinath.
This makes sure that stack allocated SSA_NAMEs are
at least MODE_ALIGNED. Also increase the MEM_ALIGN
for the corr
Hi,
The current CMSE support in the multilib build for "-march=armv8.1-m.main+mve
-mfloat-abi=hard -mfpu=auto"
is broken as specified in PR99939 and this patch fixes the issue.
Regression tested on arm-none-eabi and found no regressions.
Ok for master? and Ok for GCC-10 branch?
Regards,
Srinat
As this patch is approved here
https://gcc.gnu.org/pipermail/gcc-patches/2020-October/556387.html ,
committed to releases/gcc-10 branch.
This patch fixes (PR97327) the warning -mcpu=cortex-m55 conflicts with
-march=armv8.1-m.main
for -mfloat-abi=soft by adding the isa_bit_mve_float to clearing F
Hello,
This patch fixes (PR97327) the warning -mcpu=cortex-m55 conflicts with
-march=armv8.1-m.main
for -mfloat-abi=soft by adding the isa_bit_mve_float to clearing FP bit list.
The following combination are fixed with this patch:
$ cat bug.c
int main(){
return 0;
}
$ arm-none-eabi-gcc -mcpu=co
Hello,
Applied cleanly, Ok for backporting this patch to GCC-10?
A few MVE intrinsics had an unsigned variant implement while they are
supported by the hardware. This patch removes them:
__arm_vqrdmlashq_n_u8
__arm_vqrdmlahq_n_u8
__arm_vqdmlahq_n_u8
__arm_vqrdmlashq_n_u16
__arm_vqrdmlahq_n_u16
_
Hello,
Applied cleanly, Ok for backporting this patch to GCC-10?
This patch adds:
vqdmlashq_m_n_s16
vqdmlashq_m_n_s32
vqdmlashq_m_n_s8
vqdmlashq_n_s16
vqdmlashq_n_s32
vqdmlashq_n_s8
2020-10-08 Christophe Lyon
gcc/
PR target/96914
* config/arm/arm_mve.h (vqdmlashq, vqd
Hello,
Applied cleanly, Ok for backporting this patch to GCC-10?
__arm_vcvtnq_u32_f32 was missing from arm_mve.h, although the s32_f32 and
[su]16_f16 versions were present.
This patch adds the missing version and testcase, which are
cut-and-paste from the other versions.
2020-10-08 Christophe
This patch fixes (PR97271) the wrong code-gen for mve scatter store with
writeback intrinsics with -O2.
$cat bug.c
void
foo (uint32x4_t * addr, const int offset, int32x4_t value)
{
vstrwq_scatter_base_wb_s32 (addr, 8, value);
}
$ arm-none-eabi-gcc bug.c -S -O2 -march=armv8.1-m.main+mve -mfloa
Hello,
This patch fixes (PR97271) the wrong code-gen for mve scatter store with
writeback intrinsics with -O2.
$cat bug.c
#include "arm_mve.h"
void
foo (uint32x4_t * addr, const int offset, int32x4_t value)
{
vstrwq_scatter_base_wb_s32 (addr, 8, value);
}
$ arm-none-eabi-gcc bug.c -S -O2 -ma
Backport of Joe's patch wit no changes.
This patch rearranges feature bits for MVE and FP to implement the
following flags for -mcpu=cortex-m55.
- +nomve:equivalent to armv8.1-m.main+fp.dp+dsp.
- +nomve.fp: equivalent to armv8.1-m.main+mve+fp.dp (+dsp is implied by +mve).
- +nofp: e
Backport approved here
https://gcc.gnu.org/pipermail/gcc-patches/2020-October/555618.html .
To maintain consistency with other Arm Architectures backend, iterators and
iterator attributes are moved
from mve.md file to iterators.md. Also move enumerators for MVE unspecs from
mve.md file to unspe
Hi Kyrill,
> -Original Message-
> From: Kyrylo Tkachov
> Sent: 06 October 2020 14:42
> To: Srinath Parvathaneni ; gcc-
> patc...@gcc.gnu.org
> Subject: RE: [PATCH][GCC] arm: Move iterators from mve.md to iterators.md
> to maintain consistency.
>
>
>
> > -Original Message-
> > F
Hello,
Straight backport of Joe's patch with no changes.
This patch fixes an issue with vmin* and vmax* intrinsics which accept
a scalar argument. Previously when the scalar was of different width
to the vector elements this would generate __ARM_undef. This change
allows the scalar argument to be
Hello,
To maintain consistency with other Arm Architectures backend, iterators and
iterator attributes are moved
from mve.md file to iterators.md. Also move enumerators for MVE unspecs from
mve.md file to unspecs.md file.
Regression tested on arm-none-eabi and found no regressions.
Ok for mast
Hello,
This patch fixes (PR96795) MVE intrinsic polymorphic variants vaddq, vaddq_m,
vaddq_x, vcmpeqq_m,
vcmpeqq, vcmpgeq_m, vcmpgeq, vcmpgtq_m, vcmpgtq, vcmpleq_m, vcmpleq, vcmpltq_m,
vcmpltq,
vcmpneq_m, vcmpneq, vfmaq_m, vfmaq, vfmasq_m, vfmasq, vmaxnmavq, vmaxnmavq_p,
vmaxnmvq,
vmaxnmvq_p, v
Hello,
This patch fixes (PR96795) MVE intrinsic polymorphic variants vaddq, vaddq_m,
vaddq_x, vcmpeqq_m,
vcmpeqq, vcmpgeq_m, vcmpgeq, vcmpgtq_m, vcmpgtq, vcmpleq_m, vcmpleq, vcmpltq_m,
vcmpltq,
vcmpneq_m, vcmpneq, vfmaq_m, vfmaq, vfmasq_m, vfmasq, vmaxnmavq, vmaxnmavq_p,
vmaxnmvq,
vmaxnmvq_p, v
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