Re: [PATCH v5] AArch64: Add LUTI ACLE for SVE2

On 1/21/2025 11:37 AM, Richard Sandiford wrote: Thanks for the update. LGTM with one trivial fix: writes: diff --git a/gcc/config/aarch64/aarch64-sve-builtins-shapes.cc b/gcc/config/aarch64/aarch64-sve-builtins-shapes.cc index ca721dd2c09..d8776a55230 100644 --- a/gcc/config/aarch64/aarch64-

Re: [PATCH v3] AArch64: Add LUTI ACLE for SVE2

Hey Andrew, On 1/8/2025 12:15 PM, Andrew Carlotti wrote: On Wed, Jan 08, 2025 at 11:13:41AM +, Richard Sandiford wrote: writes: This patch introduces support for LUTI2/LUTI4 ACLE for SVE2. LUTI instructions are used for efficient table lookups with 2-bit or 4-bit indices. LUTI2 reads ind

Re: [PATCH v4] AArch64: Add LUTI ACLE for SVE2

On 1/16/2025 8:44 AM, Richard Sandiford wrote: Thanks for the update. Mostly LGTM, but some comments below: writes: diff --git a/gcc/config/aarch64/aarch64-sve2.md b/gcc/config/aarch64/aarch64-sve2.md index f8cfe08f4c0..0a1dc314f94 100644 --- a/gcc/config/aarch64/aarch64-sve2.md +++ b/gcc

Re: [PATCH v3] AArch64: Add LUTI ACLE for SVE2

On 1/8/2025 11:13 AM, Richard Sandiford wrote: writes: This patch introduces support for LUTI2/LUTI4 ACLE for SVE2. LUTI instructions are used for efficient table lookups with 2-bit or 4-bit indices. LUTI2 reads indexed 8-bit or 16-bit elements from the low 128 bits of the table vector usin

Re: [PATCH 1/3] aarch64: Add support for fp8 convert and scale

On 11/7/2024 9:03 AM, Kyrylo Tkachov wrote: Hi Saurabh, On 6 Nov 2024, at 11:03, saurabh@arm.com wrote: The AArch64 FEAT_FP8 extension introduces instructions for conversion and scaling. This patch introduces the following intrinsics: 1. vcvt{1|2}_{bf16|high_bf16|low_bf16}_mf8_fpm. 2.

Re: [PATCH v5 1/2] aarch64: Add SVE2 faminmax intrinsics

On 10/9/2024 5:26 PM, Richard Sandiford wrote: writes: +/* +** amax_0_f16_m_tied1: +** ... +** famax z0\.h, p0/m, z0\.h, (z[0-9]+\.h) Sorry to ask for another round, but: the "(" and ")" aren't needed. They're used when something later in the regular expression sequence needs to

Re: [PATCH v3 1/2] aarch64: Add SVE2 faminmax intrinsics

On 10/8/2024 3:27 PM, Richard Sandiford wrote: Saurabh Jha writes: Thanks for the review. Wanted to clarify your comment: On 10/8/2024 11:51 AM, Richard Sandiford wrote: writes: diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/amax_f16.c b/gcc/testsuite/gcc.target/aarch64

Re: [PATCH v3 1/2] aarch64: Add SVE2 faminmax intrinsics

Thanks for the review. Wanted to clarify your comment: On 10/8/2024 11:51 AM, Richard Sandiford wrote: writes: diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/amax_f16.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/amax_f16.c new file mode 100644 index 000..de4a6f8efaa

Re: [PATCH] aarch64: Fix bug with max/min (PR116934)

Thanks for the reviews. I made the suggested change in the commit message, committed, and pushed it: https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=20ce363c557d6458ec3193ab4e7df760fbe34976 Thanks, Saurabh On 10/4/2024 10:09 AM, saurabh@arm.com wrote: In ac4cdf5cb43c0b09e81760e2a1902ceebcf1

Re: [PATCH v2 2/3] aarch64: Introduce new unspecs for smax/smin

On 10/1/2024 2:07 PM, Richard Sandiford wrote: writes: Introduce two new unspecs, UNSPEC_COND_SMAX and UNSPEC_COND_SMIN, corresponding to rtl operators smax and smin. UNSPEC_COND_SMAX is used to generate fmaxnm instruction and UNSPEC_COND_SMIN is used to generate fminnm instruction. With th

Re: [PATCH v3] aarch64: Add fp8 scalar types

I just pushed it to the trunk. Thanks, Saurabh On 9/20/2024 3:09 PM, Claudio Bantaloukas wrote: The ACLE defines a new scalar type, __mfp8. This is an opaque 8bit types that can only be used by fp8 intrinsics. Additionally, the mfloat8_t type is made available in arm_neon.h and arm_sve.h as an

Re: [PATCH] aarch64: Optimise calls to ldexp with SVE FSCALE instruction

Hi Soumya, Thank you for the patch. Two clarifications: In the instruction pattern's output string, why did you add the 'Z' prefix before operands? (%0 -> %Z0). Also, maybe you can make your test cases more precise by specifying which functions generate which instructions. I don't have and S

Re: [PATCH v10 0/2] Add support for AdvSIMD faminmax

On 9/18/2024 4:28 PM, saurabh@arm.com wrote: From: Saurabh Jha This is a revised version of this patch series: https://gcc.gnu.org/pipermail/gcc-patches/2024-September/663204.html The only new thing in both patches of this series are fixing directives in test cases, replace /* { dg-do

Re: [PATCH v2] AArch64: Fix copysign patterns

On 9/20/2024 10:51 AM, Christophe Lyon wrote: Hi Saurabh, On 9/18/24 21:53, Saurabh Jha wrote: Hi Wilco, Thanks for the patch. This mostly looks good. Just added a couple clarifications. On 9/18/2024 8:17 PM, Wilco Dijkstra wrote: v2: Add more testcase fixes. The current copysign pattern

Re: [PATCH v2] AArch64: Fix copysign patterns

Hi Wilco, Thanks for the patch. This mostly looks good. Just added a couple clarifications. On 9/18/2024 8:17 PM, Wilco Dijkstra wrote: v2: Add more testcase fixes. The current copysign pattern has a mismatch in the predicates and constraints - operand[2] is a register_operand but also has a

Re: [PATCH v8 0/2] aarch64: Add support for AdvSIMD faminmax.

Ping On 9/3/2024 4:32 PM, saurabh@arm.com wrote: From: Saurabh Jha This series is a revised version of: https://gcc.gnu.org/pipermail/gcc-patches/2024-August/661860.html. The first patch of the series is updated to address these comments: https://gcc.gnu.org/pipermail/gcc-patches/2024

Re: [PATCH v3 1/2] aarch64: Add AdvSIMD faminmax intrinsics

Hi Kyrill, On 8/8/2024 4:23 PM, Kyrylo Tkachov wrote: Hi Saurabh, On 7 Aug 2024, at 17:11, saurabh@arm.com wrote: External email: Use caution opening links or attachments The AArch64 FEAT_FAMINMAX extension is optional from Armv9.2-a and mandatory from Armv9.5-a. It introduces instructi

Re: [PATCH] aarch64: Add ACLE intrinsics for AdvSIMD faminmax

Hi Kyrill, Thank you for the review. I have addressed all the comments here: https://gcc.gnu.org/pipermail/gcc-patches/2024-August/658968.html Thanks, Saurabh On 7/22/2024 12:57 PM, Kyrylo Tkachov wrote: Hi Saurabh, On 22 Jul 2024, at 13:39, saurabh@arm.com wrote: External email: Use

Re: [PATCH v2] testsuite, arm: Fix testcase arm/pr112337.c to check for the options first

Ping On 2/19/2024 10:11 AM, Saurabh Jha wrote: On 2/9/2024 2:57 PM, Richard Earnshaw (lists) wrote: On 30/01/2024 17:07, Saurabh Jha wrote: Hey, Previously, this test was added to fix this bug: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112337. However, it did not check the compilation

Re: [PATCH v2] testsuite, arm: Fix testcase arm/pr112337.c to check for the options first

On 2/9/2024 2:57 PM, Richard Earnshaw (lists) wrote: On 30/01/2024 17:07, Saurabh Jha wrote: Hey, Previously, this test was added to fix this bug: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112337. However, it did not check the compilation options before using them, leading to errors

Re: [PATCH] testsuite, arm: Fix testcase arm/pr112337.c to check for the options first

Ping. I also don't have commit access so can someone please commit on my behalf. From: Saurabh Jha Sent: Tuesday, January 30, 2024 5:07 PM To: Richard Sandiford via Gcc-patches; Richard Sandiford; Kyrylo Tkachov; Richard Earnshaw Subject: [

[PATCH] testsuite, arm: Fix testcase arm/pr112337.c to check for the options first

Hey, Previously, this test was added to fix this bug: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112337. However, it did not check the compilation options before using them, leading to errors. This patch fixes the test by first checking whether it can use the options before using them. Test

Re: [PATCH v2] testsuite, arm: Fix up pr112337.c test

On 12/1/2023 2:10 PM, Richard Earnshaw (lists) wrote: On 01/12/2023 13:45, Christophe Lyon wrote: On Fri, 1 Dec 2023 at 13:44, Richard Earnshaw (lists) wrote: On 01/12/2023 11:28, Saurabh Jha wrote: Hey, I introduced this test "gcc/testsuite/gcc.target/arm/mve/pr112337.c" in th

[PATCH] testsuite, arm: Fix up pr112337.c test

case From 2365aae84de030bbb006edac18c9314812fc657b Mon Sep 17 00:00:00 2001 From: Saurabh Jha Date: Tue, 28 Nov 2023 13:05:58 + Subject: [PATCH] testsuite: Fix up pr112337.c test --- gcc/testsuite/gcc.target/arm/mve/pr112337.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff -

Re: [PATCH] Add a REG_P check for inc and dec for Arm MVE

Hi Christophe, On 11/20/2023 10:12 AM, Christophe Lyon wrote: Hi Saurabh, On Tue, 14 Nov 2023 at 15:51, Kyrylo Tkachov wrote: Hi Saurabh, -Original Message- From: Saurabh Jha Sent: Thursday, November 9, 2023 10:12 AM To: gcc-patches@gcc.gnu.org; Richard Earnshaw ; Richard

Re: [PATCH][Binutils] AArch64: Enable Debug (FEAT_DEBUGv8p9) extension

Hey, On 11/24/2023 8:42 AM, Saurabh Jha wrote: Hey, This patch enables FEAT_DEBUGv8p9 extension for AArch64 and adds its system registers. FEAT_DEBUGv8p9 is default from Armv8.9-A Architecture. Did regression testing for aarch64-none-elf target and found no regressions. Ok for master

[PATCH][Binutils] AArch64: Enable Debug (FEAT_DEBUGv8p9) extension

ne to commit on my behalf. Regards, Saurabh From 5600438d1fb31cc9d0135b92dfe792906e9fac73 Mon Sep 17 00:00:00 2001 From: Saurabh Jha Date: Tue, 21 Nov 2023 09:50:35 + Subject: [PATCH] Enable Debug (DEBUGv8p9) extension for AArch64 --- gas/testsuite/gas/aarch64/armv8_9-a-sysregs-bad.l | 2 ++

[PATCH] Add a REG_P check for inc and dec for Arm MVE

REG_P check for INC and DEC operations From a53553878602c7050b4f027a19149ca643b11721 Mon Sep 17 00:00:00 2001 From: Saurabh Jha Date: Wed, 8 Nov 2023 14:33:35 + Subject: [PATCH 1/1] Add a REG_P check for inc and dec for Arm MVE It is okay to have operands in MEM for inc and dec in Arm MVE.

Re: [pushed] [RA]: Modify cost calculation for dealing with pseudo equivalences

Hey, This is causing an ICE. Bug here: 112337 � arm: ICE in arm_effective_regno when compiling for MVE (gnu.org) Regards, Saurabh From: Vladimir Makarov Sent: Thursday, October 26, 2023 3:00 PM To: gcc-pat

Re: [PATCH v2][GCC] aarch64: Enable Cortex-X4 CPU

On 10/6/2023 2:24 PM, Saurabh Jha wrote: Hey, This patch adds support for the Cortex-X4 CPU to GCC. Regression testing for aarch64-none-elf target and found no regressions. Okay for gcc-master? I don't have commit access so if it looks okay, could someone please help me commit

[PATCH v2][GCC] aarch64: Enable Cortex-X4 CPU

Hey, This patch adds support for the Cortex-X4 CPU to GCC. Regression testing for aarch64-none-elf target and found no regressions. Okay for gcc-master? I don't have commit access so if it looks okay, could someone please help me commit this? Thanks, Saurabh gcc/ChangeLog   * config/aar

[PATCH][GCC] aarch64: Enable Cortex-X4 CPU

Hey, This patch adds support for the Cortex-X4 CPU to GCC. Regression testing for aarch64-none-elf target and found no regressions. Okay for gcc-master? I don't have commit access so if it looks okay, could someone please help me commit this? Thanks, Saurabh gcc/ChangeLog * config/aarc

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