Please find the updated patch below. I hope I've covered everything.
I've added the test for inline restriction, could you check if I got all the
options correct?
Changelog:
2017-06-23 Prachi Godbole
gcc/
* config/mips/mips.h (machine_function): Ne
This patch adds support for function attribute __attribute__
((use_hazard_barrier_return)). The attribute will generate hazard barrier
return (jr.hb) instead of a normal return instruction.
Changelog:
2017-04-25 Prachi Godbole
gcc/
* config/mips/mips.h (machine_function): New
Committed as r245995 with dg-skip-if comment change.
Prachi
-Original Message-
From: Matthew Fortune
Sent: Thursday, March 9, 2017 2:59 PM
To: Prachi Godbole; gcc-patches@gcc.gnu.org
Cc: Moore, Catherine
Subject: RE: [PATCH][MIPS]MSA AND.d optimization to generate BCLRI.d
Prachi
Hi,
Here's a patch to disable the test for BCLRI.d optimization for level -O0.
OK for trunk?
Changelog:
2017-03-09 Prachi Godbole
gcc/testsuite/
* gcc.target/mips/msa-bclri.c: Skip the test for -O0.
Index: testsuite/gcc.target/mips/msa-bc
, fmax_a, fmin_a: RTL operand is missing mode; it was discovered
while forward propagating the result.
Fix: Introduce mode iterator in if_then_else construct.
OK?
Changelog:
2017-03-06 Prachi Godbole
gcc/
* config/mips/mips-msa.md (msa_fmax_a_, msa_fmin_a_,
msa_max_a_
Hi,
A bug was discovered in MSA dotp__d, dpadd__d and dpsub__d RTL
patterns while CSE'ing the result:
Wrong MODE for vec_select in the second mult operand.
The patch below fixes the same.
OK for trunk?
Changelog:
2017-03-06 Prachi Godbole
gcc/
* config/mips/mips-m
doubleword.
It is used by BCLRI.d alternative in AND.d pattern for immediate const vector
operand with only one bit clear.
OK?
Changelog:
2017-03-06 Prachi Godbole
gcc/
* config/mips/mips.c (mips_gen_const_int_vector): Change type of last
argument.
* config/mips/mip
absolute instruction family: Introduce mode iterator in
if_then_else construct. It enables some optimizations like CSE fwprop etc.
Tests for all of them are also included in the patch.
Ok for trunk?
Regards,
Prachi
Changelog:
2017-02-07 Prachi Godbole
gcc/
* config/mips/mips-msa.md
Sorry for all the trouble. I messed up with the Changelog by mistake. I'll be
careful now onwards.
Prachi
-Original Message-
From: Jeff Law [mailto:l...@redhat.com]
Sent: Wednesday, December 10, 2014 4:05 AM
To: Matthew Fortune; Prachi Godbole
Cc: gcc-patches@gcc.gnu.org
Subjec
Committed.
Prachi
-Original Message-
From: Matthew Fortune
Sent: Wednesday, December 3, 2014 4:18 PM
To: Prachi Godbole; gcc-patches@gcc.gnu.org
Subject: RE: [PATCH][MIPS] P5600 pipeline description fixes
> Changelog:
>
> 2014-12-03 Prachi Godbole
>
> * confi
Hi,
This patch merges automata p5600_agen_pipe and p5600_alu_pipe into one to
enable blocking of the cpu units in either-or reservations.
It also changes the order of the units in such reservations to benefit from
multi-issue scenarios.
Changelog:
2014-12-03 Prachi Godbole
Committed with ChangeLog entry fixes.
Prachi
-Original Message-
From: Matthew Fortune
Sent: Wednesday, November 5, 2014 4:07 PM
To: Prachi Godbole; gcc-patches@gcc.gnu.org
Subject: RE: [PATCH][MIPS] Fix P5600 memory cost
> The patch below fixes the memory cost for P5
PM
To: Prachi Godbole; gcc-patches@gcc.gnu.org
Subject: RE: [PATCH][MIPS] Fix P5600 memory cost
Hi Prachi,
> OK with fixes to the changelog entry:
>
> latency not latency. Remember to tab in the changelog entry and split
> the line as it will exceed 80 chars. Also two spaces between the
2014-11-06 Prachi Godbole
* MAINTAINERS (Write After Approval): Add myself.
Index: MAINTAINERS
===
--- MAINTAINERS (revision 217171)
+++ MAINTAINERS (working copy)
@@ -395,6 +395,7 @@
Tristan Gingold
Hi,
The patch below fixes the memory cost for P5600.
ChangeLog:
2014-11-05 Prachi Godbole
* config/mips/mips.c (mips_rtx_cost_data): Fix memory_letency cost for p5600.
diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index af6a913..558ba2f 100644
--- a/gcc/config/mips/mips.c
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