On Tue, Sep 06, 2022 at 12:19:06PM -0500, Segher Boessenkool wrote:
> On Mon, Sep 05, 2022 at 02:36:30PM +0800, HAO CHEN GUI wrote:
> > On 2/9/2022 下午 11:56, Segher Boessenkool wrote:
> > >> - const signed long __builtin_vsx_scalar_extract_exp (double);
> > >> + const unsigned long long __builtin
Commit eccbd7fcee5bbfc47731e8de83c44eee2e3dcc4b moved the subject file to
g++.target/powerpc. Unfortunately, test g++.dg/tsan/pr88018.C includes
"../pr69667.C".
Revert the move of this file.
Commit 14e678a2c4a76433fd4029568d28530c921e11ee relaxed some DejaGnu
directives in g++.dg/tsan/pr88018.C,
On Thu, May 12, 2022 at 05:30:16PM -0500, Segher Boessenkool wrote:
> On Mon, Apr 18, 2022 at 12:15:35PM -0500, Paul A. Clarke wrote:
> > A few tests need not be restricted to 'lp64', so remove the restriction.
> >
> > A few of those need a simple change to the DejaGnu directives to suppress
> > '
> On 12 May 2022, at 23:38, Segher Boessenkool
> wrote:
> On Mon, Apr 18, 2022 at 12:15:34PM -0500, Paul A. Clarke wrote:
>> -/* { dg-skip-if "" { powerpc*-*-darwin* } } */
>> +/* Never tested on darwin, so skip there. */
>> +/* { dg-skip-if "" { *-*-darwin* } } */
>
> That is probably the reas
ping
On Mon, Apr 18, 2022 at 12:15:33PM -0500, Paul A. Clarke via Gcc-patches wrote:
> v3: moved "not tested on Darwin" changes into 1/2, where they belong.
>
> v2:
> - v1 patches 1/3 and 2/3 have been merged after reviews / approval.
> - Previous 3/3 is now 1/2, and n
On Mon, Apr 11, 2022 at 11:23:48AM -0500, Paul A. Clarke via Gcc-patches wrote:
> In commit a2a919aa501e3 (2003), built-ins for modf and modff were added.
> In extend.texi, section "Other Builtins", "modf" was added to the paragraph
> "There are also built-in
2022-04-22 Paul A. Clarke
gcc
* doc/extend.texi: Correct "This" to "These".
---
Committed as trivial/obvious.
gcc/doc/extend.texi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index e10b10bc1f14..931e5ae3769f 100644
--- a
Also adjust DejaGnu directives, as specifically requiring "powerpc*-*-*" is no
longer required.
2021-04-18 Paul A. Clarke
gcc/testsuite
* g++.dg/pr65240.h: Move to g++.target/powerpc.
* g++.dg/pr93974.C: Likewise.
* g++.dg/pr65240-1.C: Move to g++.target/powerpc, adjust
A few tests need not be restricted to 'lp64', so remove the restriction.
A few of those need a simple change to the DejaGnu directives to suppress
'-mcmodel' flags for '-m32'.
2022-04-18 Paul A. Clarke
gcc/testsuite
* g++.target/powerpc/pr65240-1.C: Adjust DejaGnu directives.
v3: moved "not tested on Darwin" changes into 1/2, where they belong.
v2:
- v1 patches 1/3 and 2/3 have been merged after reviews / approval.
- Previous 3/3 is now 1/2, and new 2/2 is per review from Segher...
Some tests in g++.dg are target-specific for powerpc. Move those to
g++.target/powerpc.
Also adjust DejaGnu directives, as specifically requiring "powerpc*-*-*" is no
longer required.
2021-04-18 Paul A. Clarke
gcc/testsuite
* g++.dg/pr65240.h: Move to g++.target/powerpc.
* g++.dg/pr93974.C: Likewise.
* g++.dg/pr65240-1.C: Move to g++.target/powerpc, adjust
A few tests need not be restricted to 'lp64', so remove the restriction.
A few of those need a simple change to the DejaGnu directives to suppress
'-mcmodel' flags for '-m32'.
2022-04-18 Paul A. Clarke
gcc/testsuite
* g++.target/powerpc/pr65240-1.C: Adjust DejaGnu directives.
V1 patches 1/3 and 2/3 have been merged after reviews / approval.
Previous 3/3 is now 1/2, and new 2/2 is per review from Segher...
Some tests in g++.dg are target-specific for powerpc. Move those to
g++.target/powerpc. Update the DejaGnu directives as needed, since
the target restriction is perh
In commit a2a919aa501e3 (2003), built-ins for modf and modff were added.
In extend.texi, section "Other Builtins", "modf" was added to the paragraph
"There are also built-in versions of the ISO C99 functions [...]" and
"modf" was also added to the paragraph "The ISO C90 functions [...]".
"modff" wa
Ping.
On Tue, Mar 08, 2022 at 01:59:47PM -0600, Paul A. Clarke via Gcc-patches wrote:
> Ping.
>
> On Mon, Feb 21, 2022 at 03:17:47PM -0600, Paul A. Clarke via Gcc-patches
> wrote:
> > Also adjust DejaGnu directives, as specifically requiring "powerpc*-*-*" is
Ping.
On Tue, Mar 08, 2022 at 02:03:04PM -0600, Paul A. Clarke via Gcc-patches wrote:
> Gentle ping. I am grateful for the initial review, but seek closure on the
> final couple of discussion items. Thanks!
>
> PC
>
> On Tue, Feb 22, 2022 at 07:56:40PM -0600, Paul A. Clar
On Wed, Mar 23, 2022 at 05:33:21PM +0800, Kewen.Lin via Gcc-patches wrote:
> As shown in PR104967, for some overload built-in function instance,
> if it requires a date type which isn't defined on the target, its
nit: s/date/data/
> fntype would be initialized as NULL. This patch is to consider
Gentle ping. I am grateful for the initial review, but seek closure on the
final couple of discussion items. Thanks!
PC
On Tue, Feb 22, 2022 at 07:56:40PM -0600, Paul A. Clarke via Gcc-patches wrote:
> On Tue, Feb 22, 2022 at 06:41:45PM -0600, Segher Boessenkool wrote:
> > On Mon, Feb
Ping.
On Mon, Feb 21, 2022 at 03:17:47PM -0600, Paul A. Clarke via Gcc-patches wrote:
> Also adjust DejaGnu directives, as specifically requiring "powerpc*-*-*" is no
> longer required.
>
> 2021-02-21 Paul A. Clarke
>
> gcc/testsuite
> * g++.dg/debug/dwar
On Tue, Feb 22, 2022 at 06:41:45PM -0600, Segher Boessenkool wrote:
> On Mon, Feb 21, 2022 at 03:17:46PM -0600, Paul A. Clarke wrote:
> > Also adjust DejaGnu directives, as specifically requiring "powerpc*-*-*" is
> > no
> > longer required.
> >
> > 2021-02-21 Paul A. Clarke
> >
> > gcc/tests
On Tue, Feb 22, 2022 at 12:28:56PM -0600, Segher Boessenkool wrote:
> On Mon, Feb 21, 2022 at 03:17:44PM -0600, Paul A. Clarke wrote:
> > Some tests in g++.dg are target-specific for powerpc. Move those to
> > g++.target/powerpc. Update the DejaGnu directives as needed, since
> > the target restric
Also adjust DejaGnu directives, as specifically requiring "powerpc*-*-*" is no
longer required.
2021-02-21 Paul A. Clarke
gcc/testsuite
* g++.dg/debug/dwarf2/const2.C: Move to g++.target/powerpc.
* g++.dg/other/darwin-minversion-1.C: Likewise.
* g++.dg/eh/ppc64-sighandl
Also adjust DejaGnu directives, as specifically requiring "powerpc*-*-*" is no
longer required.
2021-02-21 Paul A. Clarke
gcc/testsuite
* g++.dg/ext/altivec-1.C: Move to g++.target/powerpc, adjust dg
directives.
* g++.dg/ext/altivec-2.C: Likewise.
* g++.dg/ext/a
Also adjust DejaGnu directives, as specifically requiring "powerpc*-*-*" is no
longer required.
2021-02-21 Paul A. Clarke
gcc/testsuite
* g++.dg/pr65240.h: Move to g++.target/powerpc.
* g++.dg/pr93974.C: Likewise.
* g++.dg/pr65240-1.C: Move to g++.target/powerpc, adjust
Some tests in g++.dg are target-specific for powerpc. Move those to
g++.target/powerpc. Update the DejaGnu directives as needed, since
the target restriction is perhaps no longer needed when residing in the
target-specific powerpc subdirectory.
Tested with Linux on Power9, full "make check".
OK f
On Wed, Jan 26, 2022 at 03:50:35PM -0500, David Edelsohn via Gcc-patches wrote:
> On Wed, Jan 26, 2022 at 3:45 PM Jakub Jelinek wrote:
> > r12-4717-g7d37abedf58d66 added immintrin.h and x86gprintrin.h headers
> > to rs6000, these headers are on x86 standalone headers that various
> > programs incl
This is the patch that was committed. Thanks for the review!
---
Power10 ISA added `xxblendv*` instructions which are realized in the
`vec_blendv` instrinsic.
Use `vec_blendv` for `_mm_blendv_epi8`, `_mm_blendv_ps`, and
`_mm_blendv_pd` compatibility intrinsics, when `_ARCH_PWR10`.
Update original
On Fri, Jan 07, 2022 at 02:40:51PM -0500, David Edelsohn via Gcc-patches wrote:
> +#ifdef __LITTLE_ENDIAN__
> + /* Sum across four integers with two integer results. */
> + asm ("vsum2sws %0,%1,%2" : "=v" (result) : "v" (vsum), "v" (zero));
> + /* Note: vec_sum2s could be used here, but on litt
On Fri, Jan 07, 2022 at 02:23:14PM -0500, David Edelsohn wrote:
> > Power10 ISA added `vextract*` instructions which are realized in the
> > `vec_extractm` instrinsic.
> >
> > Use `vec_extractm` for `_mm_movemask_ps`, `_mm_movemask_pd`, and
> > `_mm_movemask_epi8` compatibility intrinsics, when `_A
On Fri, Jan 07, 2022 at 02:15:22PM -0500, David Edelsohn wrote:
> > Power10 ISA added `xxblendv*` instructions which are realized in the
> > `vec_blendv` instrinsic.
> >
> > Use `vec_blendv` for `_mm_blendv_epi8`, `_mm_blendv_ps`, and
> > `_mm_blendv_pd` compatibility intrinsics, when `_ARCH_PWR10`
On Thu, Nov 18, 2021 at 08:25:35PM -0600, Paul A. Clarke via Gcc-patches wrote:
> On Mon, Nov 08, 2021 at 11:42:27AM -0600, Paul A. Clarke via Gcc-patches
> wrote:
> > Gentle ping...
>
> Gentle re-ping.
Gentle re-re-ping.
> > On Wed, Oct 20, 2021 at 08:42:07PM -0500
On Thu, Nov 18, 2021 at 08:24:52PM -0600, Paul A. Clarke via Gcc-patches wrote:
> On Mon, Nov 08, 2021 at 11:40:42AM -0600, Paul A. Clarke via Gcc-patches
> wrote:
> > On Tue, Oct 26, 2021 at 03:00:11PM -0500, Paul A. Clarke via Gcc-patches
> > wrote:
> > > Pa
Committed as trivial and obvious.
Fixes 85289ba36c2e62de84cc0232c954d9a74bda708a.
2021-12-06 Paul A. Clarke
gcc
PR target/103545
* config/rs6000/xmmintrin.h (_mm_movemask_ps): Replace "vector" with
"__vector".
---
gcc/config/rs6000/xmmintrin.h | 2 +-
1 file changed,
On Mon, Nov 08, 2021 at 11:43:26AM -0600, Paul A. Clarke via Gcc-patches wrote:
> Gentle ping...
Gentle re-ping.
> On Fri, Oct 22, 2021 at 12:28:49PM -0500, Paul A. Clarke via Gcc-patches
> wrote:
> > Power9 ISA added `vabsdub` instruction which is realized in the
> >
On Mon, Nov 08, 2021 at 11:42:56AM -0600, Paul A. Clarke via Gcc-patches wrote:
> Gentle ping...
Gentle re-ping.
> On Thu, Oct 21, 2021 at 12:22:12PM -0500, Paul A. Clarke via Gcc-patches
> wrote:
> > Power10 ISA added `vextract*` instructions which are realized in the
&g
On Mon, Nov 08, 2021 at 11:42:27AM -0600, Paul A. Clarke via Gcc-patches wrote:
> Gentle ping...
Gentile re-ping.
> On Wed, Oct 20, 2021 at 08:42:07PM -0500, Paul A. Clarke via Gcc-patches
> wrote:
> > Power10 ISA added `xxblendv*` instructions which are realized in the
On Mon, Nov 08, 2021 at 11:40:42AM -0600, Paul A. Clarke via Gcc-patches wrote:
> On Tue, Oct 26, 2021 at 03:00:11PM -0500, Paul A. Clarke via Gcc-patches
> wrote:
> > Patches 1/3 and 3/3 have been committed.
> > This is only a ping for 2/3.
>
> Gentle re-ping.
Gentle
On Wed, Nov 17, 2021 at 02:00:02PM -0600, Segher Boessenkool wrote:
> On Wed, Nov 17, 2021 at 11:45:02AM -0600, Paul A. Clarke wrote:
> > I guess I'm being pedantic. "requires -mcpu=power8 and -mvsx" is not
> > accurate from a user's point a view, as "-mcpu=power8" is sufficient,
> > since "-mvsx"
On Wed, Nov 17, 2021 at 11:00:07AM -0600, Bill Schmidt via Gcc-patches wrote:
> On 11/17/21 10:54 AM, Paul A. Clarke wrote:
> > On Tue, Nov 16, 2021 at 11:12:35AM -0600, Bill Schmidt via Gcc-patches
> > wrote:
> >> Hi! During a previous patch review, Segher asked that I provide better
> >> messag
On Tue, Nov 16, 2021 at 11:12:35AM -0600, Bill Schmidt via Gcc-patches wrote:
> Hi! During a previous patch review, Segher asked that I provide better
> messages when builtins are unavailable because they require both a minimum
> CPU and the enablement of VSX instructions. This patch does just th
Gentle ping...
On Fri, Oct 22, 2021 at 12:28:49PM -0500, Paul A. Clarke via Gcc-patches wrote:
> Power9 ISA added `vabsdub` instruction which is realized in the
> `vec_absd` instrinsic.
>
> Use `vec_absd` for `_mm_sad_epu8` compatibility intrinsic, when
> `_ARCH_PWR9`.
>
>
Gentle ping...
On Thu, Oct 21, 2021 at 12:22:12PM -0500, Paul A. Clarke via Gcc-patches wrote:
> Power10 ISA added `vextract*` instructions which are realized in the
> `vec_extractm` instrinsic.
>
> Use `vec_extractm` for `_mm_movemask_ps`, `_mm_movemask_pd`, and
> `_m
Gentle ping...
On Wed, Oct 20, 2021 at 08:42:07PM -0500, Paul A. Clarke via Gcc-patches wrote:
> Power10 ISA added `xxblendv*` instructions which are realized in the
> `vec_blendv` instrinsic.
>
> Use `vec_blendv` for `_mm_blendv_epi8`, `_mm_blendv_ps`, and
> `_mm_blendv_pd
On Tue, Oct 26, 2021 at 03:00:11PM -0500, Paul A. Clarke via Gcc-patches wrote:
> Patches 1/3 and 3/3 have been committed.
> This is only a ping for 2/3.
Gentle re-ping.
> On Mon, Oct 18, 2021 at 08:15:11PM -0500, Paul A. Clarke via Gcc-patches
> wrote:
> > Suppress exceptio
Patches 1/3 and 3/3 have been committed.
This is only a ping for 2/3.
On Mon, Oct 18, 2021 at 08:15:11PM -0500, Paul A. Clarke via Gcc-patches wrote:
> Suppress exceptions (when specified), by saving, manipulating, and
> restoring the FPSCR. Similarly, save, set, and restore the floating
On Mon, Oct 25, 2021 at 05:32:51PM -0500, Segher Boessenkool wrote:
> On Mon, Oct 25, 2021 at 03:33:21PM -0500, Paul A. Clarke wrote:
> > * config/rs6000/x86intrin.h: Move some included headers to new
> > headers; include new immintrin.h instead.
>
> s/; i/. I/ (And instead of what?)
>
Tests which only include expect many other include files
to be brought in, but not enough are.
Try to increase compatibility with x86 headers by:
- Create new immintrin.h, including the analogous subset of intrinsics
headers available for powerpc.
- Create new x86gprintrin.h, serving exclusivel
Inline functions defined in smmintrin.h need "extern" as part of their
declaration, otherwise instances of those functions are created in the
objects which include them.
Fixes commits:
- acd4b9103c1a30c833de4eee31fb69c3ff13cd77
- 9d352c68e8c8b642a36a6bcfc7f6b5dba11ac748
- bd9a8737d478f7f1d01a9d5f1
Power9 ISA added `vabsdub` instruction which is realized in the
`vec_absd` instrinsic.
Use `vec_absd` for `_mm_sad_epu8` compatibility intrinsic, when
`_ARCH_PWR9`.
Also, the realization of `vec_sum2s` on little-endian includes
two shifts in order to position the input and output to match
the sem
Power10 ISA added `vextract*` instructions which are realized in the
`vec_extractm` instrinsic.
Use `vec_extractm` for `_mm_movemask_ps`, `_mm_movemask_pd`, and
`_mm_movemask_epi8` compatibility intrinsics, when `_ARCH_PWR10`.
2021-10-21 Paul A. Clarke
gcc
* config/rs6000/xmmintrin.h
Power10 ISA added `xxblendv*` instructions which are realized in the
`vec_blendv` instrinsic.
Use `vec_blendv` for `_mm_blendv_epi8`, `_mm_blendv_ps`, and
`_mm_blendv_pd` compatibility intrinsics, when `_ARCH_PWR10`.
Also, copy a test from i386 for testing `_mm_blendv_ps`.
This should have come w
On Tue, Oct 19, 2021 at 09:32:20AM -0500, Segher Boessenkool wrote:
> On Mon, Oct 18, 2021 at 08:15:12PM -0500, Paul A. Clarke via Gcc-patches
> wrote:
> > Some compatibility implementations of x86 intrinsics include
> > Power intrinsics which require POWER8. Guard them.
Suppress exceptions (when specified), by saving, manipulating, and
restoring the FPSCR. Similarly, save, set, and restore the floating-point
rounding mode when required.
No attempt is made to optimize writing the FPSCR (by checking if the new
value would be the same), other than using lighter wei
Some compatibility implementations of x86 intrinsics include
Power intrinsics which require POWER8. Guard them.
emmintrin.h:
- _mm_cmpord_pd: Remove code which was ostensibly for pre-POWER8,
but which indeed depended on POWER8 (vec_cmpgt(v2du)/vcmpgtud).
The "POWER8" version works fine on pre
Fix an ommission in commit 29fb1e831bf1c25e4574bf2f98a9f534e5c67665.
2021-10-18 Paul A. Clarke
gcc
* config/config.gcc (extra_headers): Add nmmintrin.h.
---
gcc/config.gcc | 1 +
1 file changed, 1 insertion(+)
diff --git a/gcc/config.gcc b/gcc/config.gcc
index aa5bd5d14590..1cb9303b3
v4:
- Of original 6 patches in this series, I committed patches 2-5.
- Found an issue from v3. New file "nmmintrin.h" also needs to be added
to gcc/config.gcc "extra_headers". Unfortunately, I discovered this
after committing the patch which added "nmmintrin.h", so I've added a
new patch here.
- A
On Tue, Oct 12, 2021 at 05:25:32PM -0500, Segher Boessenkool wrote:
> On Tue, Oct 12, 2021 at 02:35:57PM -0500, Paul A. Clarke wrote:
> > static __inline __attribute__ ((__always_inline__)) void
> > libc_feholdsetround_ppc_ctx (struct rm_ctx *ctx, int r)
> > {
> > fenv_union_t old;
> > register
On Wed, Oct 13, 2021 at 06:47:21PM -0500, Segher Boessenkool wrote:
> On Wed, Oct 13, 2021 at 12:04:39PM -0500, Paul A. Clarke wrote:
> > On Mon, Oct 11, 2021 at 07:11:13PM -0500, Segher Boessenkool wrote:
> > > > - _mm_mul_epu32: vec_mule(v4su) uses vmuleuw.
> > >
> > > Did this fail on p7? If n
On Mon, Oct 11, 2021 at 07:11:13PM -0500, Segher Boessenkool wrote:
> On Mon, Aug 23, 2021 at 02:03:10PM -0500, Paul A. Clarke wrote:
> > Some compatibility implementations of x86 intrinsics include
> > Power intrinsics which require POWER8. Guard them.
>
> > emmintrin.h:
> > - _mm_cmpord_pd: Rem
On Mon, Oct 11, 2021 at 05:04:12PM -0500, Segher Boessenkool wrote:
> On Mon, Oct 11, 2021 at 12:31:07PM -0500, Paul A. Clarke wrote:
> > On Mon, Oct 11, 2021 at 11:28:39AM -0500, Segher Boessenkool wrote:
> > > > Very similar methods are used in glibc today. Are those broken?
> > >
> > > Maybe.
>
I misspelled the dg-require-effective-target attribute "vsx_hw" in
recent commits, causing the effected tests to fail. Correct the spelling.
2021-10-11 Paul A. Clarke
gcc/testsuite
* gcc.target/powerpc/pr78102.c: Fix dg-require-effective-target.
* gcc.target/powerpc/sse4_1-pac
On Mon, Oct 11, 2021 at 06:07:35PM -0500, Segher Boessenkool wrote:
> On Mon, Aug 23, 2021 at 02:03:09PM -0500, Paul A. Clarke wrote:
> > gcc
> > * config/rs6000/smmintrin.h (_mm_cmpeq_epi64, _mm_cmpgt_epi64,
> > _mm_mullo_epi32, _mm_mul_epi32, _mm_packus_epi32): New.
> > * config/rs600
On Mon, Oct 11, 2021 at 04:52:44PM -0500, Segher Boessenkool wrote:
> On Mon, Aug 23, 2021 at 02:03:08PM -0500, Paul A. Clarke wrote:
[...]
> > +extern __inline __m128i
> > +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> > +_mm_cvtepi8_epi16 (__m128i __A)
> > +{
> > + return
On Mon, Oct 11, 2021 at 03:50:31PM -0500, Segher Boessenkool wrote:
> On Mon, Aug 23, 2021 at 02:03:07PM -0500, Paul A. Clarke wrote:
> > gcc
> > * config/rs6000/smmintrin.h (_mm_test_all_zeros,
> > _mm_test_all_ones, _mm_test_mix_ones_zeros): Replace.
>
> "Replace" does not say what it is
On Mon, Oct 11, 2021 at 02:28:15PM -0500, Segher Boessenkool wrote:
> On Mon, Aug 23, 2021 at 02:03:06PM -0500, Paul A. Clarke wrote:
> > gcc
> > * config/rs6000/smmintrin.h (_mm_min_epi8, _mm_min_epu16,
> > _mm_min_epi32, _mm_min_epu32, _mm_max_epi8, _mm_max_epu16,
> > _mm_max_epi32, _
On Mon, Oct 11, 2021 at 11:28:39AM -0500, Segher Boessenkool wrote:
> On Mon, Oct 11, 2021 at 08:46:17AM -0500, Paul A. Clarke wrote:
> > On Fri, Oct 08, 2021 at 05:31:11PM -0500, Segher Boessenkool wrote:
[...]
> > > > With respect to volatile, I worry about removing it, because I do
> > > > indee
On Fri, Oct 08, 2021 at 05:31:11PM -0500, Segher Boessenkool wrote:
> On Fri, Oct 08, 2021 at 02:27:28PM -0500, Paul A. Clarke wrote:
> > On Fri, Oct 08, 2021 at 12:39:15PM -0500, Segher Boessenkool wrote:
> > I see. Thanks for the reference. If I understand correctly, volatile
> > prevents some op
On Fri, Oct 08, 2021 at 12:39:15PM -0500, Segher Boessenkool wrote:
> On Thu, Oct 07, 2021 at 08:04:23PM -0500, Paul A. Clarke wrote:
> > On Thu, Oct 07, 2021 at 06:39:06PM -0500, Segher Boessenkool wrote:
> > > > + __asm__ __volatile__ ("mffsce %0" : "=f" (__fpscr_save.__fr));
> > >
> > > Th
On Thu, Oct 07, 2021 at 06:39:06PM -0500, Segher Boessenkool wrote:
> On Mon, Aug 23, 2021 at 02:03:05PM -0500, Paul A. Clarke wrote:
> > No attempt is made to optimize writing the FPSCR (by checking if the new
> > value would be the same), other than using lighter weight instructions
> > when poss
On Thu, Oct 07, 2021 at 05:25:54PM -0500, Segher Boessenkool wrote:
> On Mon, Aug 23, 2021 at 02:03:04PM -0500, Paul A. Clarke wrote:
> > v3: Add "nmmintrin.h". _mm_cmpgt_epi64 is part of SSE4.2
>
> There should not be a "v3" in the commit message. The easy way to
> achieve this is put it inside
Ping.
On Thu, Sep 16, 2021 at 09:59:39AM -0500, Paul A. Clarke via Gcc-patches wrote:
> Ping.
>
> On Mon, Aug 23, 2021 at 02:03:04PM -0500, Paul A. Clarke via Gcc-patches
> wrote:
> > v3: Add "nmmintrin.h". _mm_cmpgt_epi64 is part of SSE4.2
> > and users
Ping.
On Mon, Aug 23, 2021 at 02:03:04PM -0500, Paul A. Clarke via Gcc-patches wrote:
> v3: Add "nmmintrin.h". _mm_cmpgt_epi64 is part of SSE4.2
> and users will expect to be able to include "nmmintrin.h",
> even though "nmmintrin.h" just includes
On Fri, Aug 27, 2021 at 08:44:43AM -0500, Bill Schmidt via Gcc-patches wrote:
> On 8/23/21 2:03 PM, Paul A. Clarke wrote:
> > + __fpscr_save.__fr = __builtin_mffsl ();
>
> As pointed out in the v1 review, __builtin_mffsl is enabled (or supposed to
> be) only for POWER9 and later. This will fail
On Fri, Aug 27, 2021 at 10:21:35AM -0500, Bill Schmidt via Gcc-patches wrote:
> On 8/23/21 2:03 PM, Paul A. Clarke wrote:
> > Function signatures and decorations match gcc/config/i386/smmintrin.h.
> > gcc
> > * config/rs6000/nmmintrin.h: Copy from i386, tweak to suit.
> > ---
> > v3:
> > - A
Suppress exceptions (when specified), by saving, manipulating, and
restoring the FPSCR. Similarly, save, set, and restore the floating-point
rounding mode when required.
No attempt is made to optimize writing the FPSCR (by checking if the new
value would be the same), other than using lighter wei
Function signatures and decorations match gcc/config/i386/smmintrin.h.
Also, copy tests for:
- _mm_cmpeq_epi64
- _mm_mullo_epi32, _mm_mul_epi32
- _mm_packus_epi32
- _mm_cmpgt_epi64 (SSE4.2)
from gcc/testsuite/gcc.target/i386.
2021-08-23 Paul A. Clarke
gcc
* config/rs6000/smmintrin.h
Function signatures and decorations match gcc/config/i386/smmintrin.h.
Also, copy tests for:
- _mm_cvtepi8_epi16, _mm_cvtepi8_epi32, _mm_cvtepi8_epi64
- _mm_cvtepi16_epi32, _mm_cvtepi16_epi64
- _mm_cvtepi32_epi64,
- _mm_cvtepu8_epi16, _mm_cvtepu8_epi32, _mm_cvtepu8_epi64
- _mm_cvtepu16_epi32, _mm_
Function signatures and decorations match gcc/config/i386/smmintrin.h.
Also, copy tests for _mm_min_epi8, _mm_min_epu16, _mm_min_epi32,
_mm_min_epu32, _mm_max_epi8, _mm_max_epu16, _mm_max_epi32, _mm_max_epu32
from gcc/testsuite/gcc.target/i386.
sse4_1-pmaxsb.c and sse4_1-pminsb.c were modified fr
v3: Add "nmmintrin.h". _mm_cmpgt_epi64 is part of SSE4.2
and users will expect to be able to include "nmmintrin.h",
even though "nmmintrin.h" just includes "smmintrin.h"
where all of the SSE4.2 implementations actually appear.
Only patch 5/6 changed from v2.
Tested ppc64le (POWER9) and ppc64/32 (
Some compatibility implementations of x86 intrinsics include
Power intrinsics which require POWER8. Guard them.
emmintrin.h:
- _mm_cmpord_pd: Remove code which was ostensibly for pre-POWER8,
but which indeed depended on POWER8 (vec_cmpgt(v2du)/vcmpgtud).
The "POWER8" version works fine on pre
Copy some simple redirections from i386 , for:
- _mm_test_all_zeros
- _mm_test_all_ones
- _mm_test_mix_ones_zeros
2021-08-20 Paul A. Clarke
gcc
* config/rs6000/smmintrin.h (_mm_test_all_zeros,
_mm_test_all_ones, _mm_test_mix_ones_zeros): Replace.
---
v3: No change.
v2:
- Remove
Some compatibility implementations of x86 intrinsics include
Power intrinsics which require POWER8. Guard them.
emmintrin.h:
- _mm_cmpord_pd: Remove code which was ostensibly for pre-POWER8,
but which indeed depended on POWER8 (vec_cmpgt(v2du)/vcmpgtud).
The "POWER8" version works fine on pre
Suppress exceptions (when specified), by saving, manipulating, and
restoring the FPSCR. Similarly, save, set, and restore the floating-point
rounding mode when required.
No attempt is made to optimize writing the FPSCR (by checking if the new
value would be the same), other than using lighter wei
Function signatures and decorations match gcc/config/i386/smmintrin.h.
Also, copy tests for:
- _mm_cvtepi8_epi16, _mm_cvtepi8_epi32, _mm_cvtepi8_epi64
- _mm_cvtepi16_epi32, _mm_cvtepi16_epi64
- _mm_cvtepi32_epi64,
- _mm_cvtepu8_epi16, _mm_cvtepu8_epi32, _mm_cvtepu8_epi64
- _mm_cvtepu16_epi32, _mm_
Function signatures and decorations match gcc/config/i386/smmintrin.h.
Also, copy tests for _mm_min_epi8, _mm_min_epu16, _mm_min_epi32,
_mm_min_epu32, _mm_max_epi8, _mm_max_epu16, _mm_max_epi32, _mm_max_epu32
from gcc/testsuite/gcc.target/i386.
sse4_1-pmaxsb.c and sse4_1-pminsb.c were modified fr
Tested ppc64le (POWER9) and ppc64/32 (POWER7).
OK for trunk?
Paul A. Clarke (6):
rs6000: Support SSE4.1 "round" intrinsics
rs6000: Support SSE4.1 "min" and "max" intrinsics
rs6000: Simplify some SSE4.1 "test" intrinsics
rs6000: Support SSE4.1 "cvt" intrinsics
rs6000: Support more SSE4.1
Function signatures and decorations match gcc/config/i386/smmintrin.h.
Also, copy tests for:
- _mm_cmpeq_epi64, _mm_cmpgt_epi64
- _mm_mullo_epi32, _mm_mul_epi32
- _mm_packus_epi32
from gcc/testsuite/gcc.target/i386.
2021-08-20 Paul A. Clarke
gcc
* config/rs6000/smmintrin.h (_mm_cmpeq
Copy some simple redirections from i386 , for:
- _mm_test_all_zeros
- _mm_test_all_ones
- _mm_test_mix_ones_zeros
2021-08-20 Paul A. Clarke
gcc
* config/rs6000/smmintrin.h (_mm_test_all_zeros,
_mm_test_all_ones, _mm_test_mix_ones_zeros): Replace.
---
v2:
- Removed "-Wno-psabi"
On Wed, Aug 18, 2021 at 05:46:58PM -0500, Segher Boessenkool wrote:
> On Mon, Aug 09, 2021 at 03:23:50PM -0500, Paul A. Clarke wrote:
> > Suppress exceptions (when specified), by saving, manipulating, and
> > restoring the FPSCR. Similarly, save, set, and restore the floating-point
> > rounding mo
Also, copy tests for:
- _mm_cmpeq_epi64, _mm_cmpgt_epi64
- _mm_mullo_epi32, _mm_mul_epi32
- _mm_packus_epi32
from gcc/testsuite/gcc.target/i386.
2021-08-09 Paul A. Clarke
gcc
* config/rs6000/smmintrin.h (_mm_cmpeq_epi64, _mm_cmpgt_epi64,
_mm_mullo_epi32, _mm_mul_epi32, _mm_pac
Also, copy tests for:
- _mm_cvtepi8_epi16, _mm_cvtepi8_epi32, _mm_cvtepi8_epi64
- _mm_cvtepi16_epi32, _mm_cvtepi16_epi64
- _mm_cvtepi32_epi64,
- _mm_cvtepu8_epi16, _mm_cvtepu8_epi32, _mm_cvtepu8_epi64
- _mm_cvtepu16_epi32, _mm_cvtepu16_epi64
- _mm_cvtepu32_epi64
from gcc/testsuite/gcc.target/i386.
Copy some simple redirections from i386 , for:
- _mm_test_all_zeros
- _mm_test_all_ones
- _mm_test_mix_ones_zeros
2021-08-09 Paul A. Clarke
gcc
* config/rs6000/smmintrin.h (_mm_test_all_zeros,
_mm_test_all_ones, _mm_test_mix_ones_zeros): Replace.
---
gcc/config/rs6000/smmintri
Suppress exceptions (when specified), by saving, manipulating, and
restoring the FPSCR. Similarly, save, set, and restore the floating-point
rounding mode when required.
No attempt is made to optimize writing the FPSCR (by checking if the new
value would be the same), other than using lighter wei
Also, copy tests for _mm_min_epi8, _mm_min_epu16, _mm_min_epi32,
_mm_min_epu32, _mm_max_epi8, _mm_max_epu16, _mm_max_epi32, _mm_max_epu32
from gcc/testsuite/gcc.target/i386.
sse4_1-pmaxsb.c and sse4_1-pminsb.c were modified from using
"char" types to "signed char" types, because the default is uns
Paul A. Clarke (6):
rs6000: Support SSE4.1 "round" intrinsics
rs6000: Support SSE4.1 "min" and "max" intrinsics
rs6000: Simplify some SSE4.1 "test" intrinsics
rs6000: Support SSE4.1 "cvt" intrinsics
rs6000: Support more SSE4.1 "cmp", "mul", "pack" intrinsics
rs6000: Guard some x86 intri
Some compatibility implementations of x86 intrinsics include
Power intrinsics which require POWER8. Guard them.
emmintrin.h:
- _mm_cmpord_pd: Remove code which was ostensibly for pre-POWER8,
but which indeed depended on POWER8 (vec_cmpgt(v2du)/vcmpgtud).
The "POWER8" version works fine on pre
On Mon, Aug 02, 2021 at 05:29:08PM -0500, Segher Boessenkool wrote:
> On Thu, Jul 15, 2021 at 06:29:17PM -0500, Paul A. Clarke wrote:
> > Add a naive implementation of the subject x86 intrinsic to
> > ease porting.
>
> > --- a/gcc/config/rs6000/smmintrin.h
> > +++ b/gcc/config/rs6000/smmintrin.h
>
On Wed, Jul 28, 2021 at 05:16:32PM -0500, Segher Boessenkool wrote:
> On Fri, Jul 16, 2021 at 08:50:20AM -0500, Paul A. Clarke wrote:
> > --- /dev/null
> > +++ b/gcc/testsuite/gcc.target/powerpc/sse4_1-round.h
> > @@ -0,0 +1,27 @@
> > +#include
> > +#include
> > +#include "sse4_1-check.h"
> > +
>
On Tue, Jul 27, 2021 at 10:29:13PM -0400, David Edelsohn via Gcc-patches wrote:
> > Add a naive implementation of the subject x86 intrinsic to
> > ease porting.
> >
> > 2021-07-15 Paul A. Clarke
> >
> > gcc
> > * config/rs6000/smmintrin.h (_mm_minpos_epu16): New.
>
> Segher already appr
Add the tests for _mm_floor_pd, _mm_floor_ps, _mm_floor_sd, _mm_floor_ss.
These are modelled after (and depend upon parts of) the tests for
_mm_ceil intrinsics, recently posted.
Copy a test for _mm_floor_sd from gcc/testsuite/gcc.target/i386.
2021-07-16 Paul A. Clarke
gcc/testsuite
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