Re: [PATCH] RISC-V: Fix riscv_modes_tieable_p

On Fri, 10 Jan 2025 12:21:15 PST (-0800), jeffreya...@gmail.com wrote: On 1/10/25 12:11 PM, Robin Dapp wrote: Integer values and floating-point values need to be converted by fmv series instructions. So if mode1 is MODE_INT and mode2 is MODE_FLOAT, we should return false in riscv_modes_tieable

Re: [PATCH 0/3] testsuite: RISC-V: Improve support for RV32E

t some specific E sub-targets you're interested in then we should probably get them added to CI, though we're in a bit of a CI resourcing crunch right now so it might be a slower process than normal... I think Jeff already said something (they're at least marked as "

Re: [PATCH] Add RISC-V/rv64gc as a secondary platform

On Fri, 20 Dec 2024 12:54:54 PST (-0800), jeffreya...@gmail.com wrote: On 12/20/24 9:48 AM, Palmer Dabbelt wrote: On Thu, 19 Dec 2024 15:01:26 PST (-0800), jeffreya...@gmail.com wrote: On 12/19/24 3:08 PM, Palmer Dabbelt wrote: I agree lacking B and V makes us very clearly uncompetitive

Re: [PATCH] Add RISC-V/rv64gc as a secondary platform

On Fri, 20 Dec 2024 09:09:02 PST (-0800), richard.guent...@gmail.com wrote: Am 20.12.2024 um 17:49 schrieb Palmer Dabbelt : On Thu, 19 Dec 2024 15:01:26 PST (-0800), jeffreya...@gmail.com wrote: On 12/19/24 3:08 PM, Palmer Dabbelt wrote: I agree lacking B and V makes us very clearly

Re: [PATCH] Add RISC-V/rv64gc as a secondary platform

On Thu, 19 Dec 2024 15:01:26 PST (-0800), jeffreya...@gmail.com wrote: On 12/19/24 3:08 PM, Palmer Dabbelt wrote: I agree lacking B and V makes us very clearly uncompetitive in the space where these sort of things matter (ie, binary compatible distros and long term stability type things

Re: [PATCH] Add RISC-V/rv64gc as a secondary platform

On Wed, 18 Dec 2024 08:20:46 PST (-0800), jeffreya...@gmail.com wrote: On 12/17/24 5:11 PM, Palmer Dabbelt wrote: This came up on IRC this morning and we talked a bit on the patchwork call this morning. I'm not really sure what the right answer is here, but it seems at least reasonab

[PATCH] Add RISC-V/rv64gc as a secondary platform

This came up on IRC this morning and we talked a bit on the patchwork call this morning. I'm not really sure what the right answer is here, but it seems at least reasonable to talk about -- we've got a lot more testing these days are we've been somewhat reasonable about following the release stage

Re: [PATCH] RISC-V: Remove svvptc from riscv-ext-bitmask.def

f @@ -79,6 +79,5 @@ RISCV_EXT_BITMASK ("zcd", 1, 4) RISCV_EXT_BITMASK ("zcf",1, 5) RISCV_EXT_BITMASK ("zcmop", 1, 6) RISCV_EXT_BITMASK ("zawrs", 1, 7) -RISCV_EXT_BITMASK ("svvptc", 1, 8) #und

Re: [PATCH] RISC-V: Fix compress shuffle pattern [PR117383].

On Wed, 11 Dec 2024 13:29:29 PST (-0800), Robin Dapp wrote: Hi, this patch makes vcompress use the tail-undisturbed policy by default and also uses the proper VL. Regtested on rv64gcv and waiting for the CI. Regards Robin PR target/117383 gcc/ChangeLog: * config/riscv/riscv

Re: [PATCH 1/3] testsuite: RISC-V: Explicitly specify ABI when adding V and Zvbb options

On Mon, 09 Dec 2024 09:05:10 PST (-0800), Robin Dapp wrote: +/* { dg-additional-options "-mabi=lp64d" { target { rv64 } } } */ +/* { dg-additional-options "-mabi=ilp32d" { target { rv32 } } } */ Wouldn't skipping those tests also be reasonable? I.e. adding a target to the compile directive inst

Re: [PATCH 2/2] RISC-V: Support RISC-V Profiles RVA/B23.

On Tue, 03 Dec 2024 03:02:47 PST (-0800), jia...@iscas.ac.cn wrote: This patch introduces support for RISC-V Profiles RV23A and RV23B [1], enabling developers to utilize these profiles through the -march option. [1] https://github.com/riscv/riscv-profiles/releases/tag/rva23-rvb23-v0.7-ratificat

Re: [PATCH] RISC-V: Add implication for M extension.

On Wed, 09 Oct 2024 09:55:02 PDT (-0700), jeffreya...@gmail.com wrote: On 10/9/24 10:52 AM, Palmer Dabbelt wrote: On Tue, 08 Oct 2024 16:43:13 PDT (-0700), jeffreya...@gmail.com wrote: On 10/7/24 11:33 PM, Tsung Chun Lin wrote: That M implies Zmmul. gcc/ChangeLog: * common

Re: [PATCH] RISC-V: Add implication for M extension.

On Tue, 08 Oct 2024 16:43:13 PDT (-0700), jeffreya...@gmail.com wrote: On 10/7/24 11:33 PM, Tsung Chun Lin wrote: That M implies Zmmul. gcc/ChangeLog: * common/config/riscv/riscv-common.cc: M implies Zmmul. THanks. I've pushed this to the trunk. jeff ps. Quite a discussion on t

Re: [PATCH] RISC-V/libgcc: Fix incorrect .cfi_offset for saving ra in __riscv_save_[0-3] on ilp32e.

On Fri, 04 Oct 2024 07:04:59 PDT (-0700), jeffreya...@gmail.com wrote: On 10/4/24 1:23 AM, Tsung Chun Lin wrote: 0001-RISC-V-libgcc-Fix-incorrect-.cfi_offset-for-saving-r.patch From 8b3c5ebe8aacbcc4ddf1be8dea9a555e7e1bcc39 Mon Sep 17 00:00:00 2001 From: Jim Lin Date: Fri, 4 Oct 2024 14:48:1

Re: [PATCH] RISC-V: Bugfix for Duplicate entries for -mtune in --target-help[Bug 116347]

On Sat, 07 Sep 2024 10:32:07 PDT (-0700), jeffreya...@gmail.com wrote: On 8/25/24 8:03 PM, Jiawei wrote: 在 2024/8/25 23:38, Jeff Law 写道: On 8/19/24 2:14 AM, shiyul...@iscas.ac.cn wrote: From: yulong This patch try to fix a bug[116347]. I change the name of the micro- arch, because I thi

Re: Subject: [PATCH 0/8] Masked load else operand.

On Sun, 11 Aug 2024 14:00:27 PDT (-0700), Robin Dapp wrote: > I figured it's easier to parse this as a series rather than one big > patch, in particular since target-specific code is involved. > > This adds an else operand to masked-load operations in order to avoid > implicit dependencies on zeroe

Re: [PATCH 6/8] gcn: Add else operand to masked loads.

On Thu, 05 Sep 2024 14:57:06 PDT (-0700), a...@baylibre.com wrote: On Thu, 5 Sept 2024, 21:10 Robin Dapp, wrote: > > +(define_predicate "maskload_else_operand" > > + (and (match_code "const_int,const_vector") > > + (match_test "op == CONST0_RTX (GET_MODE (op))"))) > > This forces masklo

Re: [PATCH] RISC-V: Define LOGICAL_OP_NON_SHORT_CIRCUIT to 1 [PR116615]

On Thu, 05 Sep 2024 11:52:57 PDT (-0700), Palmer Dabbelt wrote: We have cheap logical ops, so let's just move this back to the default to take advantage of the standard branch/op hueristics. gcc/ChangeLog: PR target/116615 * config/riscv/riscv.h (LOGICAL_OP_NON_SHORT_CI

[PATCH] RISC-V: Define LOGICAL_OP_NON_SHORT_CIRCUIT to 1 [PR116615]

We have cheap logical ops, so let's just move this back to the default to take advantage of the standard branch/op hueristics. gcc/ChangeLog: PR target/116615 * config/riscv/riscv.h (LOGICAL_OP_NON_SHORT_CIRCUIT): Remove. --- There's a bunch more discussion in the bug, but it's st

Re: [to-be-committed][V2][RISC-V] Avoid unnecessary extensions after sCC insns

On Thu, 05 Sep 2024 11:03:18 PDT (-0700), jeffreya...@gmail.com wrote: So the first patch failed the pre-commit CI; it didn't fail in my testing because I'm using --with-arch to set a default configuration that includes things like zicond to ensure that's always tested. And the failing test is

Re: [RISCV] target-specific source placement

[Sorry I crossed the streams here, I had to run out in the middle of writing up that other reply.] On Thu, 05 Sep 2024 10:49:47 PDT (-0700), jeffreya...@gmail.com wrote: On 9/5/24 8:27 AM, Nathan Sidwell wrote: Hi, looking at the RISCV code, it seems that there are several vendor- specific f

Re: [RISCV] target-specific source placement

On Thu, 05 Sep 2024 07:27:57 PDT (-0700), nat...@acm.org wrote: Hi, looking at the RISCV code, it seems that there are several vendor-specific files in config/riscv. For instance sifive-7.md and xiangshan.md. It seems these are unconditionally included for all riscv targets. I guess then one doe

Re: [PATCH] RISC-V: Make the setCC/REE tests robust to instruction selection

On Wed, 04 Sep 2024 15:20:45 PDT (-0700), jeffreya...@gmail.com wrote: On 9/4/24 4:07 PM, Palmer Dabbelt wrote: These tests were checking that the output of the setCC instruction was bit flipped, but it looks like they're really designed to test that redundant sign extension elimination

Re: [RFC PATCH] RISC-V: Add support for LP64DV

et lucky and this will trick a friendly glibc release maintainer into doing it for us... ;) On Thu, Sep 5, 2024 at 6:56 AM Jeff Law wrote: On 9/4/24 2:26 PM, Palmer Dabbelt wrote: > Now that we've got the riscv_vector_cc attribute it's pretty much free > to add a system-wide ABI -

Re: [to-be-committed][RISC-V] Avoid unnecessary extensions after sCC insns

cted case of the setCC. > Anyway, this has gone through my tester on rv32 and rv64. I'll let it > spin in the pre-commit tester before taking further action. Reviewed-by: Palmer Dabbelt Acked-by: Palmer Dabbelt Thanks! > > Jeff > > gcc/ > * config/riscv/riscv.cc (ri

[PATCH] RISC-V: Make the setCC/REE tests robust to instruction selection

These tests were checking that the output of the setCC instruction was bit flipped, but it looks like they're really designed to test that redundant sign extension elimination fires on conditionals from function inputs. Jeff just posed a patch to clean this code up with trips up on the arbitrary x

Re: [RFC PATCH] RISC-V: Add support for LP64DV

On Wed, 04 Sep 2024 13:26:11 PDT (-0700), Palmer Dabbelt wrote: Now that we've got the riscv_vector_cc attribute it's pretty much free to add a system-wide ABI -- at least in terms of implementation. So this just adds a new ABI command-line value that defaults to enabling the vect

[RFC PATCH] RISC-V: Add support for LP64DV

Now that we've got the riscv_vector_cc attribute it's pretty much free to add a system-wide ABI -- at least in terms of implementation. So this just adds a new ABI command-line value that defaults to enabling the vector calling convention, essentially the same as scattering the attribute on every

Re: [PATCH] RISC-V: Handle unused-only-live stmts in SLP discovery

On Wed, 04 Sep 2024 04:10:52 PDT (-0700), rguent...@suse.de wrote: The following adds SLP discovery for roots that are only live but otherwise unused. These are usually inductions. This allows a few more testcases to be handled fully with SLP, for example gcc.dg/vect/no-scevccp-pr86725-1.c Boo

Re: [PATCH v4] RISC-V: Supports Profiles in '-march' option.

e can The advantage is that it just side-steps all these word games about what compatibility means. On Wed, Sep 4, 2024 at 6:49 AM Palmer Dabbelt wrote: On Tue, 20 Aug 2024 23:18:36 PDT (-0700), jia...@iscas.ac.cn wrote: > > 在 2024/8/21 3:23, Palmer Dabbelt 写道: >> On Mon, 19 Aug 2

Re: [PATCH v4] RISC-V: Supports Profiles in '-march' option.

On Tue, 20 Aug 2024 23:18:36 PDT (-0700), jia...@iscas.ac.cn wrote: 在 2024/8/21 3:23, Palmer Dabbelt 写道: On Mon, 19 Aug 2024 21:53:54 PDT (-0700), jia...@iscas.ac.cn wrote: Supports RISC-V profiles[1] in -march option. Default input set the profile before other formal extensions. V2: Fixes

Re: [PATCH v4] RISC-V: Supports Profiles in '-march' option.

On Mon, 19 Aug 2024 21:53:54 PDT (-0700), jia...@iscas.ac.cn wrote: Supports RISC-V profiles[1] in -march option. Default input set the profile before other formal extensions. V2: Fixes some format errors and adds code comments for parse function Thanks for Jeff Law's review and comments. V3:

Re: [PATCH] RISC-V: Fix format-diag warning from improperly formatted url

If you need LP64E please notify the GCC project via https://gcc.gnu.org/PR116152"; "" { target *-*-* } 0 } */ +/* { dg-note "if you need LP64E please notify the GCC project via PR116152" "" { target *-*-* } 0 } */ int main () { #if !defined(__riscv) Reviewed-by: Palmer Dabbelt Acked-by: Palmer Dabbelt Thanks!

Re: [PATCH v2] RISC-V: xtheadmemidx: Fix mode test for pre/post-modify addressing

On Thu, 25 Jul 2024 08:37:05 PDT (-0700), christoph.muell...@vrull.eu wrote: On Thu, Jul 25, 2024 at 5:19 PM Palmer Dabbelt wrote: On Thu, 25 Jul 2024 08:10:25 PDT (-0700), jeffreya...@gmail.com wrote: > > > On 7/25/24 9:06 AM, Christoph Müllner wrote: >> Ok, also to backport t

Re: [PATCH v2] RISC-V: xtheadmemidx: Fix mode test for pre/post-modify addressing

On Thu, 25 Jul 2024 08:10:25 PDT (-0700), jeffreya...@gmail.com wrote: On 7/25/24 9:06 AM, Christoph Müllner wrote: Ok, also to backport to GCC 14? Yes, of course. I'm OK with that, but according to the latest status report , we're

Re: [PATCH v2] RISC-V: Error early with V and no M extension.

ion requires the % extension"); It's really GCC's implementation of the V extension that requires M, not the actul ISA V extension. So I think the wording could be a little confusing for users here, but no big deal either way on my end so Reviewed-by: Palmer

Re: [PATCH v3] RISC-V: Implement __init_riscv_feature_bits, __riscv_feature_bits, and __riscv_vendor_feature_bits

On Mon, 22 Jul 2024 07:16:28 PDT (-0700), kito.ch...@sifive.com wrote: This provides a common abstraction layer to probe the available extensions at run-time. These functions can be used to implement function multi-versioning or to detect available extensions. The advantages of providing this ab

Re: [PATCH] RISC-V: Implement __init_riscv_features_bits, __riscv_feature_bits, and __riscv_vendor_feature_bits

On Tue, 16 Jul 2024 07:49:13 PDT (-0700), kito.ch...@sifive.com wrote: This provides a common abstraction layer to probe the available extensions at run-time. These functions can be used to implement function multi-versioning or to detect available extensions. The advantages of providing this ab

[RFC PATCH] cse: Add another CSE pass after split1

This is really more of a question than a patch. Looking at PR/115687 I managed to convince myself there's a general class of problems here: splitting might produce constant subexpressions, but as far as I can tell there's nothing to eliminate those constant subexpressions. So I very quickly threw

Re: [PATCH] RISC-V: Add support for Zabha extension

On Wed, 26 Jun 2024 08:50:57 PDT (-0700), Andrea Parri wrote: Tested using amo.exp with rv64gc_zalrsc, rv64id_zaamo, rv64id_zalrsc, rv64id_zabha (using tip-of-tree qemu w/ zabha patches [2] applied for execution tests). My interpretation of the Zabha specification, in particular of "The Zabha e

Re: [PATCH] RISC-V: Support -m[no-]unaligned-access

On Fri, 22 Dec 2023 01:23:13 PST (-0800), wangpengcheng...@bytedance.com wrote: These two options are negative alias of -m[no-]strict-align. This matches LLVM implmentation. gcc/ChangeLog: * config/riscv/riscv.opt: Add option alias. gcc/testsuite/ChangeLog: * gcc.target/riscv/predef-align-10

Re: [PATCH] RISC-V: Add configure check for Zaamo/Zalrsc assembler support

On Wed, 12 Jun 2024 16:56:09 PDT (-0700), Patrick O'Neill wrote: On 6/12/24 16:49, Sam James wrote: Palmer Dabbelt writes: On Wed, 12 Jun 2024 16:20:26 PDT (-0700), Patrick O'Neill wrote: Binutils 2.42 and before don't support Zaamo/Zalrsc. Add a configure check to prevent

Re: [PATCH] RISC-V: Add configure check for Zaamo/Zalrsc assembler support

't support the subsets? That'd avoid a forced binutils bump, but really user should be upgrading anyway... Either way Acked-by: Palmer Dabbelt # RISC-V Reviewed-by: Palmer Dabbelt # RISC-V though I'm not suer if the configure churn is sane, it looks like a version mismatch

Re: [Committed] RISC-V: Add basic Zaamo and Zalrsc support

On Wed, 12 Jun 2024 10:09:06 PDT (-0700), Patrick O'Neill wrote: On 6/12/24 04:21, Andreas Schwab wrote: On Jun 12 2024, Li, Pan2 wrote: Do we need to upgrade the binutils of the riscv-gnu-toolchain repo? Or we may have unknown prefixed ISA extension `zaamo' when building. There needs to be

Re: [PATCH] RISC-V: Add min/max patterns for ifcvt.

On Mon, 03 Jun 2024 11:50:54 PDT (-0700), jeffreya...@gmail.com wrote: On 6/3/24 11:03 AM, Palmer Dabbelt wrote: +;; Provide a minmax pattern for ifcvt to match. +(define_insn "*_cmp_3" +  [(set (match_operand:X 0 "register_operand" "

Re: [PATCH] RISC-V: Add min/max patterns for ifcvt.

(match_operand:X 2 "reg_or_0_operand" "rJ")))] "TARGET_ZBB" "\t%0,%1,%z2" [(set_attr "type" "")]) but it looks like it ends up with the same types after all the iterators (there's some "max vs smax" and "s

Re: [PATCH v2] RISC-V: Introduce -mrvv-allow-misalign.

On Fri, 24 May 2024 16:50:52 PDT (-0700), jeffreya...@gmail.com wrote: On 5/24/24 5:43 PM, Palmer Dabbelt wrote: I'm only reading Zicclsm as saying both scalar and vector misaligned accesses are supported, but nothing about the performance. I think it was in the vector docs.  It didn&

Re: [PATCH v2] RISC-V: Introduce -mrvv-allow-misalign.

On Fri, 24 May 2024 16:41:39 PDT (-0700), jeffreya...@gmail.com wrote: On 5/24/24 5:39 PM, Palmer Dabbelt wrote: On Fri, 24 May 2024 16:31:48 PDT (-0700), jeffreya...@gmail.com wrote: On 5/24/24 11:14 AM, Palmer Dabbelt wrote: On Fri, 24 May 2024 09:19:09 PDT (-0700), Robin Dapp wrote

Re: [PATCH v2] RISC-V: Introduce -mrvv-allow-misalign.

On Fri, 24 May 2024 16:31:48 PDT (-0700), jeffreya...@gmail.com wrote: On 5/24/24 11:14 AM, Palmer Dabbelt wrote: On Fri, 24 May 2024 09:19:09 PDT (-0700), Robin Dapp wrote: We should have something in doc/invoke too, this one is going to be tricky for users.  We'll also have to defin

Re: [PATCH v2] RISC-V: Introduce -mrvv-allow-misalign.

On Fri, 24 May 2024 09:19:09 PDT (-0700), Robin Dapp wrote: We should have something in doc/invoke too, this one is going to be tricky for users. We'll also have to define how this interacts with the existing -mstrict-align. Addressed the rest in the attached v2 which also fixes tests. I'm rea

Re: [PATCH] RISC-V: Introduce -mrvv-allow-misalign.

On Fri, 24 May 2024 07:30:20 PDT (-0700), Robin Dapp wrote: Hi, this patch changes the default from always enabling movmisalign to disabling it. It adds an option to override the default and adds generic-ooo to the uarchs that support misaligned vector access. It also adds a check_effective_ta

Re: RISC-V: Fix round_32.c test on RV32

On Wed, 22 May 2024 12:02:26 PDT (-0700), jeffreya...@gmail.com wrote: On 5/22/24 12:15 PM, Palmer Dabbelt wrote: On Wed, 22 May 2024 11:01:16 PDT (-0700), jeffreya...@gmail.com wrote: On 5/22/24 6:47 AM, Jivan Hakobyan wrote: After 8367c996e55b2 commit several checks on round_32.c test

Re: RISC-V: Fix round_32.c test on RV32

On Wed, 22 May 2024 11:01:16 PDT (-0700), jeffreya...@gmail.com wrote: On 5/22/24 6:47 AM, Jivan Hakobyan wrote: After 8367c996e55b2 commit several checks on round_32.c test started to fail. The reason is that we prevent rounding DF->SI->DF on RV32 and instead of a conversation sequence we get

Re: [PATCH] RISC-V: Split vwadd.wx and vwsub.wx and add helpers.

On Fri, 17 May 2024 15:37:43 PDT (-0700), juzhe.zh...@rivai.ai wrote: I think it should be backport to GCC-14 since it is a bug. Seems reasonable to me -- I guess in theory those extended scalar patterns aren't bug fixes and we should split them out, but I don't think it's all that big of a d

Re: [committed][wwwdocs] gcc-12/changes.html: Document RISC-V changes

On Fri, 17 May 2024 14:30:49 PDT (-0700), ger...@pfeifer.com wrote: On Thu, 28 Apr 2022, Kito Cheng wrote: --- htdocs/gcc-12/changes.html | 13 - : +New ISA extension support for vector and scalar crypto was added, only + support architecture testing marco and -march= pa

[PATCH gcc-13] Fix RISC-V missing stack tie

From: Jeff Law As some of you know, Raphael has been working on stack-clash support for the RISC-V port. A little while ago Florian reached out to us with an issue where glibc was failing its smoke test due to referencing an unallocated stack slot. Without diving into the code in detail I (inco

[PATCH] RISC-V: Implement -m{,no}fence-tso

Some processors from T-Head don't implement the `fence.tso` instruction natively and instead trap to firmware. This breaks some users who haven't yet updated the firmware and one could imagine it breaking users who are trying to build firmware if they're using the C memory model. So just add an o

Re: Follow up #1 (was Re: [PATCH v2 1/2] RISC-V: avoid LUI based const materialization ... [part of PR/106265])

On Mon, 13 May 2024 16:08:21 PDT (-0700), Vineet Gupta wrote: On 5/13/24 15:47, Jeff Law wrote: On 5/13/24 11:49, Vineet Gupta wrote: 500.perlbench_r-0 | 1,214,534,029,025 | 1,212,887,959,387 | 500.perlbench_r-1 |740,383,419,739 | 739,280,308,163 | 500.perlbench_r-2 |692,074,

[PATCH gcc-13-backport] RISCV: Add -m(no)-omit-leaf-frame-pointer support.

From: Yanzhang Wang gcc/ChangeLog: * config/riscv/riscv.cc (riscv_save_reg_p): Save ra for leaf when enabling -mno-omit-leaf-frame-pointer (riscv_option_override): Override omit-frame-pointer. (riscv_frame_pointer_required): Save s0 for non-leaf function (

Re: [committed] [RISC-V] Allow uarchs to set TARGET_OVERLAP_OP_BY_PIECES_P

On Tue, 07 May 2024 14:18:36 PDT (-0700), Jeff Law wrote: > This is almost exclusively work from the VRULL team. > > As we've discussed in the Tuesday meeting in the past, we'd like to have > a knob in the tuning structure to indicate that overlapped stores during > move_by_pieces expansion of memc

Re: [PATCH][risc-v] libstdc++: Preserve signbit of nan when converting float to double [PR113578]

27;d need some different twiddling. Either way, I think having the signed-NaN-preserving conversion is reasonable as it's what users are going to expect (even if it's only recommended by IEEE). So Reviewed-by: Palmer Dabbelt Acked-by: Pal

Re: [PATCH v1] RISC-V: Adjust overlap attr after revert d3544cea63d and e65aaf8efe1

On Tue, 23 Apr 2024 07:45:03 PDT (-0700), Patrick O'Neill wrote: Hi Pan, Sorry about that. It looks like there was difference between my local machine and CI machine. From the CI it looks like we're back to the failure list we had on friday. I'll do some local testing to manually confirm this

Re: Re: [PATCH v1] RISC-V: Revert RVV wv instructions overlap and xfail tests

On Mon, 22 Apr 2024 15:07:59 PDT (-0700), juzhe.zh...@rivai.ai wrote: Apologize that we didn't post our (me, kito and Li Pan) disscussions. Some amount of off-list discussion is inevitable, but as far as I can tell here we ended up with some code committed that wasn't even posted to the lists

Re: [PATCH] Spelling fixes for translatable strings

he ISA-dependent CSR are only valid when the specific ISA is set. The read-only CSR can not be written by the CSR instructions. This came up on IRC. Acked-by: Palmer Dabbelt Reviewed-by: Palmer Dabbelt In case you want to merge it with the rest of thus, but I think it should be something more

[PATCH] RISC-V: Revert this weekend's changes

Looks like we had a bunch of commits over the weekend that didn't get tested/reviewed. Some didn't even make it to the lists so it's hard to tell exactly what happened, but the result was a trunk that doesn't even build and a bunch of ICEs after some trivial fix ups landed on the lists. So let's

Re: [PATCH v1] RISC-V: Adjust overlap attr after revert d3544cea63d and e65aaf8efe1

On Mon, 22 Apr 2024 06:47:34 PDT (-0700), pan2...@intel.com wrote: From: Pan Li After we reverted below 2 commits, the reference to attr need some adjustment as the group_overlap is no longer available. * RISC-V: Robostify the W43, W86, W87 constraint enabled attribute * RISC-V: Rename vconstr

Re: [PATCH] Regenerate opt.urls

On Fri, 12 Apr 2024 12:25:42 PDT (-0700), tschwi...@baylibre.com wrote: Hi! After having received around a dozen more buildbot notifications... On 2024-04-10T06:46:04-0700, Palmer Dabbelt wrote: On Tue, 09 Apr 2024 07:57:24 PDT (-0700), ishitatsuy...@gmail.com wrote: Fixes: 97069657c4e

Re: [PATCH] wwwdocs: gcc-14: Add RISC-V changes

c-ooo). + SiFive's P400 series (sifive-p400-series). + SiFive's P600 series (sifive-p600-series). + XiangShan's Nanhu microarchitecture (xiangshan-nanhu). + + + Thanks for doing this. This all pretty minor wording stuff, so Reviewed-by: Palmer Dabbelt Acked-by: Palmer Dabbelt Maybe next year we'll remember to ask submitters for these ;)

Re: [PATCH] Regenerate opt.urls

On Wed, 10 Apr 2024 00:57:59 PDT (-0700), sch...@suse.de wrote: On Apr 09 2024, Palmer Dabbelt wrote: I didn't actually regenerate this as I can't figure out how, make regenerate-opt-urls Ya, that's what the CI says too. I think I might just have a broken build tree, som

Re: [PATCH] Regenerate opt.urls

nts are the same, but I didn't actually run the regenerate script. So Reviewed-by: Palmer Dabbelt Acked-by: Palmer Dabbelt

Re: [PATCH v2 2/3] aarch64: Add support for aarch64-gnu (GNU/Hurd on AArch64)

On Tue, 09 Apr 2024 09:57:11 PDT (-0700), buga...@gmail.com wrote: On Tue, Apr 9, 2024 at 7:24 PM Palmer Dabbelt wrote: > I assume the buildbot failure that I just got an email about is > unrelated; it's failing on some RISC-V thing. Sorry if I missed something here, do you hav

[PATCH] Regenerate opt.urls

I didn't actually regenerate this as I can't figure out how, I've just pasted in the diff from the sourceware buildbot (which is complaining about post-regeneration diff). Fixes: 97069657c4e ("RISC-V: Implement TLS Descriptors.") gcc/ChangeLog: * config/riscv/riscv.opt.urls: Regenerated.

Re: [PATCH v2 2/3] aarch64: Add support for aarch64-gnu (GNU/Hurd on AArch64)

On Tue, 09 Apr 2024 01:04:34 PDT (-0700), buga...@gmail.com wrote: On Tue, Apr 9, 2024 at 10:27 AM Thomas Schwinge wrote: Thanks, pushed to trunk branch: - commit 532c57f8c3a15b109a46d3e2b14d60a5c40979d5 "Move GNU/Hurd startfile spec from config/i386/gnu.h to config/gnu.h" - commit 9670a2

Re: [gcc-13 backport PATCH] RISC-V: Fix C23 (...) functions returning large aggregates [PR114175]

On Thu, 04 Apr 2024 07:37:56 PDT (-0700), ja...@redhat.com wrote: On Thu, Apr 04, 2024 at 07:28:40AM -0700, Palmer Dabbelt wrote: I'm not sure if we need release maintainer approval, For cherry-picking one's own non-risky bugfixes for regression or documentation bugs from trunk

Re: [gcc-13 backport PATCH] RISC-V: Fix C23 (...) functions returning large aggregates [PR114175]

amp;local_cum), arg); /* Found out how many registers we need to save. */ Acked-by: Palmer Dabbelt I'm not sure if we need release maintainer approval, all I can find is the 13.2.1 status report saying 13.3 is expected in the spring <https://inbox.sourceware.org/gcc/ZMJeq

Re:[PATCH v2 1/1] [RISC-V] Add support for _Bfloat16

On Tue, 02 Apr 2024 20:19:16 PDT (-0700), ji...@linux.alibaba.com wrote: gcc/testsuite/ChangeLog: * gcc.target/riscv/bf16_arithmetic.c: New test. * gcc.target/riscv/bf16_call.c: New test. * gcc.target/riscv/bf16_comparison.c: New test. * gcc.target/riscv/bf16_floa

Re: [committed] RISC-V: Add missing insn types to XiangShan Nanhu scheduler model

On Sun, 31 Mar 2024 09:53:46 PDT (-0700), Jeff Law wrote: The test for the recently added XiangShan Nanhu microarchitecture is failing because the scheduler description does not have entries for certain insn types. I'm adding branch, jalr, ret and sfb_alu to the scheduler description, that's en

[PATCH] RISC-V: Add vxsat as a register

We aren't doing anything with vxsat right now, but I'd like to add it as an accepted register to the clobber list. If we get this into GCC-14 then we'll avoid some preprocessor-based twiddling if we ever start using vxsat in the future. gcc/ChangeLog: * config/riscv/riscv.h (REGISTER_NAM

Re: TARGET_RTX_COSTS and pipeline latency vs. variable-latency instructions (was Re: [PATCH] RISC-V: Add XiangShan Nanhu microarchitecture.)

On Mon, 25 Mar 2024 13:49:18 PDT (-0700), jeffreya...@gmail.com wrote: On 3/25/24 2:31 PM, Palmer Dabbelt wrote: On Mon, 25 Mar 2024 13:27:34 PDT (-0700), Jeff Law wrote: I'd doubt it's worth the complexity.  Picking some reasonable value gets you the vast majority of t

Re: TARGET_RTX_COSTS and pipeline latency vs. variable-latency instructions (was Re: [PATCH] RISC-V: Add XiangShan Nanhu microarchitecture.)

On Mon, 25 Mar 2024 13:27:34 PDT (-0700), Jeff Law wrote: On 3/25/24 2:13 PM, Palmer Dabbelt wrote: On Mon, 25 Mar 2024 12:59:14 PDT (-0700), Jeff Law wrote: On 3/25/24 1:48 PM, Xi Ruoyao wrote: On Mon, 2024-03-18 at 20:54 -0600, Jeff Law wrote: +/* Costs to use when optimizing for

Re: TARGET_RTX_COSTS and pipeline latency vs. variable-latency instructions (was Re: [PATCH] RISC-V: Add XiangShan Nanhu microarchitecture.)

On Mon, 25 Mar 2024 12:59:14 PDT (-0700), Jeff Law wrote: On 3/25/24 1:48 PM, Xi Ruoyao wrote: On Mon, 2024-03-18 at 20:54 -0600, Jeff Law wrote: +/* Costs to use when optimizing for xiangshan nanhu.  */ +static const struct riscv_tune_param xiangshan_nanhu_tune_info = { +  {COSTS_N_INSNS (3)

Re: [PATCH] RISC-V: Require a extension for ztso testcases with atomic insns

gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-5.c +++ b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-5.c @@ -1,5 +1,6 @@ /* { dg-do compile } */ /* Verify that subword atomic op mappings match the Ztso suggested mapping. */ +/* { dg-add-options riscv_a } */ /* { dg-add-options riscv_ztso } */ /* { dg-final { scan-assembler-times "lr.w.aqrl\t" 1 } } */ /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */ Presumably these trip up on the non-A targets that Edwin's just adding to the testers? They'd also trip up anyone running newlib/mulilib tests. Either way they look right to me, so Reviewed-by: Palmer Dabbelt Acked-by: Palmer Dabbelt Thanks!

Re: RISC-V: Use convert instructions instead of calling library functions

On Wed, 20 Mar 2024 11:54:34 PDT (-0700), Jeff Law wrote: On 3/19/24 10:23 AM, Palmer Dabbelt wrote: On Mon, 18 Mar 2024 20:50:14 PDT (-0700), jeffreya...@gmail.com wrote: On 3/18/24 3:09 AM, Jivan Hakobyan wrote: As RV has round instructions it is reasonable to use them instead of

Re: [gcc-15 2/3] RISC-V: avoid LUI based const mat: keep stack offsets aligned

On Tue, 19 Mar 2024 13:05:54 PDT (-0700), Vineet Gupta wrote: On 3/19/24 06:10, Jeff Law wrote: On 3/19/24 12:48 AM, Andrew Waterman wrote: On Mon, Mar 18, 2024 at 5:28 PM Vineet Gupta wrote: On 3/16/24 13:21, Jeff Law wrote: | 59944:add s0,sp,2047 < | 59948:mv a2

Re: RISC-V: Use convert instructions instead of calling library functions

On Tue, 19 Mar 2024 12:58:41 PDT (-0700), Andrew Waterman wrote: On Tue, Mar 19, 2024 at 9:23 AM Palmer Dabbelt wrote: On Mon, 18 Mar 2024 20:50:14 PDT (-0700), jeffreya...@gmail.com wrote: > > > On 3/18/24 3:09 AM, Jivan Hakobyan wrote: >> As RV has round instructions it is re

Re: RISC-V: Use convert instructions instead of calling library functions

On Mon, 18 Mar 2024 20:50:14 PDT (-0700), jeffreya...@gmail.com wrote: On 3/18/24 3:09 AM, Jivan Hakobyan wrote: As RV has round instructions it is reasonable to use them instead of calling the library functions. With my patch for the following C code: double foo(double a) {     return ceil(

Re: [PATCH] RISC-V: Update test expectancies with recent scheduler change

On Wed, 28 Feb 2024 02:24:40 PST (-0800), Robin Dapp wrote: I suggest specify -fno-schedule-insns to force tests assembler never change for any scheduling model. We already do that and that's the point - as I mentioned before, no scheduling is worse than default scheduling here (for some defini

Re: [PATCH] RISC-V: Fix __atomic_compare_exchange with 32 bit value on RV64

On Wed, 28 Feb 2024 09:36:38 PST (-0800), Patrick O'Neill wrote: On 2/28/24 07:02, Palmer Dabbelt wrote: On Wed, 28 Feb 2024 06:57:53 PST (-0800), jeffreya...@gmail.com wrote: On 2/28/24 05:23, Kito Cheng wrote: atomic_compare_and_swapsi will use lr.w and sc.w to do the atomic operati

Re: [PATCH] RISC-V: Fix __atomic_compare_exchange with 32 bit value on RV64

On Wed, 28 Feb 2024 06:57:53 PST (-0800), jeffreya...@gmail.com wrote: On 2/28/24 05:23, Kito Cheng wrote: atomic_compare_and_swapsi will use lr.w and sc.w to do the atomic operation on RV64, however lr.w is doing sign extend to DI and compare instruction only have DI mode on RV64, so the expe

Re: [PATCH] RISC-V: Update test expectancies with recent scheduler change

On Tue, 27 Feb 2024 15:53:19 PST (-0800), jeffreya...@gmail.com wrote: On 2/27/24 15:56, 钟居哲 wrote: >> I don't think it's that simple.  On some uarchs vsetvls are nearly free while on others they can be fairly expensive.  It's not clear (to me) yet if one approach or the other is going to be

Re: [PATCH] RISC-V: Point our Python scripts at python3

On Thu, 22 Feb 2024 20:29:37 PST (-0800), Kito Cheng wrote: I guess Palmer is too busy, so committed to trunk :P Thanks, I got distracted with some work stuff ;) On Tue, Feb 13, 2024 at 11:55 PM Jeff Law wrote: On 2/9/24 09:53, Palmer Dabbelt wrote: > This builds for me, an

Re: [PATCH v1] RISC-V: Upgrade RVV intrinsic version to 0.12

On Wed, 21 Feb 2024 16:02:50 PST (-0800), Kito Cheng wrote: Palmer Dabbelt 於 2024年2月22日 週四 07:42 寫道： On Wed, 21 Feb 2024 15:34:32 PST (-0800), Kito Cheng wrote: > LGTM for the patch > > Li, Pan2 於 2024年2月21日 週三 12:31 寫道： > >> Hi kito and juzhe. >> >> There may

Re: [PATCH v1] RISC-V: Upgrade RVV intrinsic version to 0.12

On Wed, 21 Feb 2024 15:34:32 PST (-0800), Kito Cheng wrote: LGTM for the patch Li, Pan2 於 2024年2月21日 週三 12:31 寫道： Hi kito and juzhe. There may be 2 items for double-confirm. Thanks a lot. 1. Not very sure if we need to upgrade the version for __riscv_th_v_intrinsic. Yes since 0.11 and 0.

[PATCH] doc: RISC-V: Document that -mcpu doesn't override -march or -mtune

d-off-by: Palmer Dabbelt --- gcc/doc/invoke.texi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 6ec56493e59..4a4bba9f1cd 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -30670,6 +30670,8 @@ Permissible values for this optio

[PATCH] RISC-V: Point our Python scripts at python3

This builds for me, and I frequently have python-is-python3 type packages installed so I think I've been implicitly testing it for a while. Looks like Kito's tested similar configurations, and the bugzilla indicates we should be moving over. gcc/ChangeLog: PR 109668 * config/risc

Re: [PATCH] RISC-V: Fix rvv intrinsic pragma tests dejagnu selector

e/pragma-3.c @@ -1,4 +1,4 @@ /* { dg-do compile } */ -/* { dg-skip-if "test rvv intrinsic" { *-*-* } { "*" } { "-march=rv*v*" } } */ +/* { dg-skip-if "test rvv intrinsic" { ! riscv_v } */ #pragma riscv intrinsic "report-error" /* { dg-error {unknown '#pragma riscv intrinsic' option 'report-error'} } */ Reviewed-by: Palmer Dabbelt

Re: [PATCH] RISC-V: Don't make Ztso imply A

On Wed, 24 Jan 2024 16:19:06 PST (-0800), jeffreya...@gmail.com wrote: On 1/24/24 17:07, Patrick O'Neill wrote: On 12/16/23 10:58, Jeff Law wrote: On 12/15/23 17:14, Andrew Waterman wrote: On Fri, Dec 15, 2023 at 1:38 PM Jeff Law wrote: On 12/12/23 20:54, Palmer Dabbelt wrot

Re: [PATCH] match: Do not select to branchless expression when target has movcc pattern [PR113095]

On Wed, 17 Jan 2024 19:19:58 PST (-0800), monk.chi...@sifive.com wrote: Thanks for your advice!! I agree it should be fixed in the RISC-V backend when expansion. On Wed, Jan 17, 2024 at 10:37 PM Jeff Law wrote: On 1/17/24 05:14, Richard Biener wrote: > On Wed, 17 Jan 2024, Monk Chiang wrot

Re: [committed] RISC-V: Add crypto vector builtin function.

On Thu, 04 Jan 2024 19:17:21 PST (-0800), juzhe.zh...@rivai.ai wrote: Hi, Wang Feng. Your patch has some ICEs: FAIL: gcc.target/riscv/rvv/base/zvbc-intrinsic.c (internal compiler error: RTL check: expected code 'const_int', have 'reg' in vlmax_avl_type_p, at config/riscv/riscv-v.cc:4930) FAIL:

Re: [PATCH]middle-end: Don't apply copysign optimization if target does not implement optab [PR112468]

On Thu, 04 Jan 2024 10:20:25 PST (-0800), tamar.christ...@arm.com wrote: > Hi All, > > currently GCC does not treat IFN_COPYSIGN the same as the copysign tree expr. > The latter has a libcall fallback and the IFN can only do optabs. > > Because of this the change I made to optimize copysign only wo

  1   2   3   4   5   6   >