[PATCH] RISC-V: optimization on checking certain bits set ((x & mask) == val)

lity expression, a plus pattern is matched instead. 2024-12-16 Oliver Kozul   PR target/114087 gcc/ChangeLog:   * config/riscv/riscv.md (*lui_constraint_and_to_or): New pattern gcc/testsuite/ChangeLog:   * gcc.target/riscv/pr114087-1.c: New test. CONFIDENTIALITY: The contents of th

Re: [PATCH] RISC-V: optimization on checking certain bits set ((x & mask) == val)

nday, December 15, 2024 1:19 AM To: Oliver Kozul ; gcc-patches@gcc.gnu.org Cc: Dusan Stojkovic ; Mile Davidovic ; l...@gcc.gnu.org Subject: Re: [PATCH] RISC-V: optimization on checking certain bits set ((x & mask) == val) On 12/6/24 6:12 AM, Oliver Kozul wrote: > The patch optimizes code

[PATCH] RISC-V: optimization by converting to LUI operands with LUI_AFTER_COMMON_LEADING_SHIFT

The patch optimizes code generation for comparisons of the form X & C1 == C2. When the bitwise AND mask is stored in the lower 20 bits it can be left shifted so it behaves as a LUI operand instead, saving an addi instruction while loading. 2024-12-13 Oliver Kozul   PR target/114087

[PATCH] RISC-V: optimization by converting LUI operands with SMALL_AFTER_COMMON_TRAILING_SHIFT

using 12 bits, which is advantageous in RISC-V, since instructions such as ANDI exist. By shifting all used values by 20 bits to the right, we can make use of the “and immediate” instruction, thus improving performance. 2024-12-11 Oliver Kozul   PR target/114087 gcc/ChangeLog:   * config/

[PATCH] RISC-V: optimization on checking certain bits set ((x & mask) == val)

The patch optimizes code generation for comparisons of the form X & C1 == C2 by converting them to (X | ~C1) == (C2 | ~C1). C1 is a constant that requires li and addi to be loaded, while ~C1 requires a single lui instruction. 2024-12-06 Oliver Kozul   PR target/114087 gcc/Chang