[PATCH v4 6/7] RISC-V: Fix matches against subreg with a bytenum of 0 in riscv.md

These all intend the least significant subpart of the register. Use the same endian-neutral "subreg_lowpart_operator" predicate that ARM does instead. gcc/ * config/riscv/predicates.md (subreg_lowpart_operator): New predicate * config/riscv/riscv.md (*addsi3_extended2, *subsi3_exte

[PATCH v4 7/7] RISC-V: Fix riscv_subword() for big endian

gcc/ * config/riscv/riscv.c (riscv_subword): Take endianness into account when calculating the byte offset. --- gcc/config/riscv/riscv.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c index 1cd795bd19c..2f624e

[PATCH v4 5/7] RISC-V: Update shift-shift-5.c testcase for big endian

gcc/ * testsuite/gcc.target/riscv/shift-shift-5.c (sub): Change order of struct fields depending on byteorder. --- gcc/testsuite/gcc.target/riscv/shift-shift-5.c | 4 1 file changed, 4 insertions(+) diff --git a/gcc/testsuite/gcc.target/riscv/shift-shift-5.c b/gcc/testsuite/

[PATCH v4 4/7] RISC-V: Fix trampoline generation on big endian

gcc/ * config/riscv/riscv.c (riscv_swap_instruction): New function to byteswap an SImode rtx containing an instruction. (riscv_trampoline_init): Byteswap the generated instructions when needed. --- gcc/config/riscv/riscv.c | 19 +++ 1 file changed, 1

[PATCH v4 3/7] RISC-V: Update soft-fp config for big-endian

libgcc/ * config/riscv/sfp-machine.h (__BYTE_ORDER): Set according to __BYTE_ORDER__. --- libgcc/config/riscv/sfp-machine.h | 4 1 file changed, 4 insertions(+) diff --git a/libgcc/config/riscv/sfp-machine.h b/libgcc/config/riscv/sfp-machine.h index db2697157ce..8adbf4b8b2e

[PATCH v4 2/7] RISC-V: Add riscv{32,64}be with big endian as default

gcc/ * common/config/riscv/riscv-common.c (TARGET_DEFAULT_TARGET_FLAGS): Set default endianness. * config.gcc (riscv32be-*, riscv64be-*): Set TARGET_BIG_ENDIAN_DEFAULT to 1. * config/riscv/elf.h (LINK_SPEC): Change -melf* value depending on default en

[PATCH v4 1/7] RISC-V: Support -mlittle-endian and -mbig-endian

gcc/ * config/riscv/elf.h (LINK_SPEC): Pass linker endianness flag. * config/riscv/freebsd.h (LINK_SPEC): Likewise. * config/riscv/linux.h (LINK_SPEC): Likewise. * config/riscv/riscv.h (ASM_SPEC): Pass -mbig-endian and -mlittle-endian. (BYTES_BIG_ENDI

[PATCH v4 0/7] RISC-V big endian support

New update of the RISC-V big endian support. Changes since v3: * Changed riscv_subword to take endianness into account. This fixed multiple issues with long long on 32-bit. Testsuite results are now on par with little endian also on 32 bit. The only exception is gcc.c-torture/

Re: [PATCH v2 0/5] RISC-V big endian support

Hello again Kito. I've now delved a bit deeper into the failure of the testcase gcc.c-torture/compile/pr35318.c on big endian RV32. The point at which big endian diverges from little endian is where process_alt_operands() is processing the "%0" constraint. It calls operands_match_p(), which su

Re: [PATCH v2 0/5] RISC-V big endian support

Hi Kito. I fixed almost all of the rv32be testcase failures simply by taking endianness into account on the first line of riscv_subword, which is used for long long handling on 32-bit. Now, I only have one failing testcase (which does not also fail on little endian), and it's a doozy. The test

[PATCH v3 6/6] RISC-V: Fix matches against subreg with a bytenum of 0 in riscv.md

These all intend the least significant subpart of the register. Use the same endian-neutral "subreg_lowpart_operator" predicate that ARM does instead. gcc/ * config/riscv/predicates.md (subreg_lowpart_operator): New predicate * config/riscv/riscv.md (*addsi3_extended2, *subsi3_exte

[PATCH v3 5/6] RISC-V: Update shift-shift-5.c testcase for big endian

gcc/ * testsuite/gcc.target/riscv/shift-shift-5.c (sub): Change order of struct fields depending on byteorder. --- gcc/testsuite/gcc.target/riscv/shift-shift-5.c | 4 1 file changed, 4 insertions(+) diff --git a/gcc/testsuite/gcc.target/riscv/shift-shift-5.c b/gcc/testsuite/

[PATCH v3 4/6] RISC-V: Fix trampoline generation on big endian

gcc/ * config/riscv/riscv.c (riscv_swap_instruction): New function to byteswap an SImode rtx containing an instruction. (riscv_trampoline_init): Byteswap the generated instructions when needed. --- gcc/config/riscv/riscv.c | 19 +++ 1 file changed, 1

[PATCH v3 3/6] RISC-V: Update soft-fp config for big-endian

libgcc/ * config/riscv/sfp-machine.h (__BYTE_ORDER): Set according to __BYTE_ORDER__. --- libgcc/config/riscv/sfp-machine.h | 4 1 file changed, 4 insertions(+) diff --git a/libgcc/config/riscv/sfp-machine.h b/libgcc/config/riscv/sfp-machine.h index db2697157ce..8adbf4b8b2e

[PATCH v3 2/6] RISC-V: Add riscv{32,64}be with big endian as default

gcc/ * common/config/riscv/riscv-common.c (TARGET_DEFAULT_TARGET_FLAGS): Set default endianness. * config.gcc (riscv32be-*, riscv64be-*): Set TARGET_BIG_ENDIAN_DEFAULT to 1. * config/riscv/elf.h (LINK_SPEC): Change -melf* value depending on default en

[PATCH v3 1/6] RISC-V: Support -mlittle-endian and -mbig-endian

gcc/ * config/riscv/elf.h (LINK_SPEC): Pass linker endianness flag. * config/riscv/freebsd.h (LINK_SPEC): Likewise. * config/riscv/linux.h (LINK_SPEC): Likewise. * config/riscv/riscv.h (ASM_SPEC): Pass -mbig-endian and -mlittle-endian. (BYTES_BIG_ENDI

[PATCH v3 0/6] RISC-V big endian support

New update of the RISC-V big endian support. Changes since v2: * Replaced matches of (subreg ... 0) in riscv.md with calls to a predicate "subreg_lowpart_operator", modeled on how arm.md and aarch64.md works. Testsuite result on 64-bit is now rv64gc/ lp64/ med

Re: [PATCH v2 0/5] RISC-V big endian support

Hi again. I've found the reason for the shift-and test fails. riscv.md does a match on (subreg:QI (and:SI ...) 0) Unfortunately, due to the way "subreg" is defined, this needs to be (subreg:QI (and:SI ...) 3) on big endian. I can fix the failures by duplicating the rule and making the

Re: [PATCH v2 0/5] RISC-V big endian support

Hi Kito, Kito Cheng writes: > I just spend some time on those two testcase, I think this those two > testcase could just skip in big-endinan. Well, that sounds like a pretty big cop out. If the software doesn't behave like we expect it too I feel we should at least have some idea _why_...

Re: [PATCH v2 0/5] RISC-V big endian support

Hi Kito, Kito Cheng writes: > FAIL: gcc.c-torture/execute/string-opt-5.c > FAIL: gcc.target/riscv/shift-and-1.c scan-assembler-not andi > FAIL: gcc.target/riscv/shift-and-2.c scan-assembler-not andi string-opt-5.c is one of the newlib issues I mentioned (handcoded assembler for strcmp which a

[PATCH v2 5/5] RISC-V: Update shift-shift-5.c testcase for big endian

gcc/ * testsuite/gcc.target/riscv/shift-shift-5.c (sub): Change order of struct fields depending on byteorder. --- gcc/testsuite/gcc.target/riscv/shift-shift-5.c | 4 1 file changed, 4 insertions(+) diff --git a/gcc/testsuite/gcc.target/riscv/shift-shift-5.c b/gcc/testsuite/

[PATCH v2 4/5] RISC-V: Fix trampoline generation on big endian

gcc/ * config/riscv/riscv.c (riscv_swap_instruction): New function to byteswap an SImode rtx containing an instruction. (riscv_trampoline_init): Byteswap the generated instructions when needed. --- gcc/config/riscv/riscv.c | 19 +++ 1 file changed, 1

[PATCH v2 3/5] RISC-V: Update soft-fp config for big-endian

libgcc/ * config/riscv/sfp-machine.h (__BYTE_ORDER): Set according to __BYTE_ORDER__. --- libgcc/config/riscv/sfp-machine.h | 4 1 file changed, 4 insertions(+) diff --git a/libgcc/config/riscv/sfp-machine.h b/libgcc/config/riscv/sfp-machine.h index db2697157ce..8adbf4b8b2e

[PATCH v2 2/5] RISC-V: Add riscv{32,64}be with big endian as default

gcc/ * common/config/riscv/riscv-common.c (TARGET_DEFAULT_TARGET_FLAGS): Set default endianness. * config.gcc (riscv32be-*, riscv64be-*): Set TARGET_BIG_ENDIAN_DEFAULT to 1. * config/riscv/elf.h (LINK_SPEC): Change -melf* value depending on default en

[PATCH v2 1/5] RISC-V: Support -mlittle-endian and -mbig-endian

gcc/ * config/riscv/elf.h (LINK_SPEC): Pass linker endianness flag. * config/riscv/freebsd.h (LINK_SPEC): Likewise. * config/riscv/linux.h (LINK_SPEC): Likewise. * config/riscv/riscv.h (ASM_SPEC): Pass -mbig-endian and -mlittle-endian. (BYTES_BIG_ENDI

[PATCH v2 0/5] RISC-V big endian support

This is an update to the patch series for big endian RISC-V support. Changes since last version: * Added documentation of -mbig-endian and -mlittle-endian * New patch: Fix soft-fp endianness setting * New patch: Fix trampoline generation on big endian * New patch: Update the shift-shif

Re: [PATCH 0/2] RISC-V big endian support

Hi Kito, Kito Cheng writes: > I tried to run with gcc testsuite on spike + pk, seems got a bunch > extra fail cases, > could you take a look for that? Looking at it now. I'm getting a large number of failures in floating point tests, which turn out to be due to a newlib problem; newlib/libc/

Re: [PATCH 2/2] RISC-V: Add riscv{32, 64}be with big endian as default

Hi again. Sorry, but I just realized that the "-melf" part isn't the same in all of {elf,linux,freebsd}.h; linux.h has a LD_EMUL_SUFFIX which the other two are lacking. Which means that the only truly common part is %{mbig-endian:-EB} \ %{mlittle-endian:-EL} \ So is it worth a define to c

Re: [PATCH 2/2] RISC-V: Add riscv{32, 64}be with big endian as default

Kito Cheng writes: > Yeah, but I'd like to include following 2 lines too: > > %{mbig-endian:-EB} \ > %{mlittle-endian:-EL} \ > > I saw it's just the same among 3 files. Ah, I see. Then it becomes a little more of a mixed grab bag. I see that SuperH has a spec "subtarget_link_spec" which incl

Re: [PATCH 2/2] RISC-V: Add riscv{32, 64}be with big endian as default

Kito Cheng writes: >> diff --git a/gcc/config/riscv/elf.h b/gcc/config/riscv/elf.h >> index 973efdaed7b..7e65e499031 100644 >> --- a/gcc/config/riscv/elf.h >> +++ b/gcc/config/riscv/elf.h >> @@ -18,7 +18,7 @@ along with GCC; see the file COPYING3. If not see >> .

Re: [PATCH 1/2] RISC-V: Support -mlittle-endian and -mbig-endian

Kito Cheng writes: > Could you document -mbig-endian and -mlittle-endian in gcc/doc/invoke.texi? Sure, I'll add that. // Marcus

Re: [PATCH 0/2] RISC-V big endian support

Hi Kito, Kito Cheng writes: > You can add a check in configure.ac and config.in to detect whether > binutils is supported or not. > here is example, search HAVE_AS_MISA_SPEC in this patch: > https://github.com/gcc-mirror/gcc/commit/4b81528241ca682025d92558ff6aeec91dafdca8 Ok, but I specifical

[PATCH 2/2] RISC-V: Add riscv{32,64}be with big endian as default

gcc/ * common/config/riscv/riscv-common.c (TARGET_DEFAULT_TARGET_FLAGS): Set default endianness. * config.gcc (riscv32be-*, riscv64be-*): Set TARGET_BIG_ENDIAN_DEFAULT to 1. * config/riscv/elf.h (LINK_SPEC): Change -melf* value depending on default en

[PATCH 1/2] RISC-V: Support -mlittle-endian and -mbig-endian

gcc/ * config/riscv/elf.h (LINK_SPEC): Pass linker endianness flag. * config/riscv/freebsd.h (LINK_SPEC): Likewise. * config/riscv/linux.h (LINK_SPEC): Likewise. * config/riscv/riscv.h (ASM_SPEC): Pass -mbig-endian and -mlittle-endian. (BYTES_BIG_ENDI

[PATCH 0/2] RISC-V big endian support

Greetings. Big endian support for RISC-V was added in binutils 2.36, released yesterday. This patch set adds support to gcc for exploting this mode. Please note that in addition to these patches, an pull of config.sub from upstreams is needed. In adding the big endian support, I had the followi