New update of the RISC-V big endian support. Changes since v2:
* Replaced matches of (subreg ... 0) in riscv.md with calls to
a predicate "subreg_lowpart_operator", modeled on how
arm.md and aarch64.md works.
Testsuite result on 64-bit is now
rv64gc/ lp64/ medlow | 12 / 6 | 39 / 10 | - |
on both big-endian and little-endian.
On 32-bit I'm seeing a lot of
User store segfault @ 0x7f7fffff
in the execution tests. Need to investigate this further.
// Marcus
