Re: [PATCH 2/7] libstdc++: Make __normal_iterator constexpr, always_inline, nodiscard

Clang appears to be a bit picky wrt the relative order of annotation notations here, and complains /home/sberg/gcc/inst/lib/gcc/x86_64-pc-linux-gnu/15.0.0/../../../../include/c++/15.0.0/bits/stl_iter ator.h:1080:42: error: an attribute list cannot appear here 1080 | __attribute__((__

[r13-9139 Regression] FAIL: gcc.target/i386/avx512bw-pr103750-2.c scan-assembler-not kmov on Linux/x86_64

On Linux/x86_64, fca35b417c236e3448bc3666820fd1ba423fe6e9 is the first bad commit commit fca35b417c236e3448bc3666820fd1ba423fe6e9 Author: liuhongt Date: Wed Oct 16 13:43:48 2024 +0800 Refine splitters related to "combine vpcmpuw + zero_extend to vpcmpuw" caused FAIL: gcc.target/i386/avx5

[PATCH]middle-end: Handle more gcond lowering [PR117176]

Hi All, For boolean mask handling we have to lower BIT_NOT_EXPR for correctness into BIT_XOR_EXPR. Normally this is done through vect_recog_bool_pattern by following the defs of the gimple_assign. In the PR we ICE because early exits have the comparison inside the gcond itself and so vect_recog_

Re: [PATCH] Add fancy pointer support in std::map/set

On 17/10/2024 23:11, Jonathan Wakely wrote: On Thu, 17 Oct 2024 at 21:39, Jonathan Wakely wrote: On Thu, 17 Oct 2024 at 20:52, François Dumont wrote: Here is an updated version that compiles, I think, all your feedbacks. It's much cleaner indeed. Thanks, I

Re: [PATCH v4] libstdc++: implement concatenation of strings and string_views

On 17/10/2024 11:13, Giuseppe D'Angelo wrote: Hello, Il 17/10/24 06:32, François Dumont ha scritto: As a side note you should provide your patches as .txt files so that any email client can render it without going through an editor. Apologies for that. Do you mean I should use text/plain at

[PATCH 2/2] RISC-V: Add testcases for unsigned .SAT_SUB form 1 with IMM = 1.

From: xuli form 1: T __attribute__((noinline)) \ sat_u_sub_imm##IMM##_##T##_fmt_1 (T y) \ { \ return (T)IMM >= y ? (T)IMM - y : 0; \ } Passed the rv64gcv regression test. Change-Id: I8805225b445cdbbc685f4f54a4d66c7ee8f748e1 Signed-off-by: Li

[PATCH 1/2] Match: Support IMM=1 for unsigned scalar .SAT_SUB IMM form 1

From: xuli This patch would like to support .SAT_SUB when one of the op is IMM = 1 of form1. Form 1: #define DEF_SAT_U_SUB_IMM_FMT_1(T, IMM) \ T __attribute__((noinline)) \ sat_u_sub_imm##IMM##_##T##_fmt_1 (T y) \ { \ return IMM >= y ? IM

[PATCH 2/2] RISC-V: Add testcases for unsigned .SAT_SUB form 1 with IMM = max -1.

From: xuli form 1: T __attribute__((noinline)) \ sat_u_sub_imm##IMM##_##T##_fmt_1 (T y) \ { \ return (T)IMM >= y ? (T)IMM - y : 0; \ } Passed the rv64gcv regression test. gcc/testsuite/ChangeLog: * gcc.target/riscv/sat_u_sub_imm-1_3

[PATCH 1/2] Match: Support IMM=max-1 for unsigned scalar .SAT_SUB IMM form 1

From: xuli This patch would like to support .SAT_SUB when one of the op is IMM = max - 1 of form1. Form 1: #define DEF_SAT_U_SUB_IMM_FMT_1(T, IMM) \ T __attribute__((noinline)) \ sat_u_sub_imm##IMM##_##T##_fmt_1 (T y) \ { \ return IMM >=

Re: [PATCH] fold fold_truth_andor field merging into ifcombine

On Oct 10, 2024, Richard Biener wrote: > Thanks for working on this. There's #if 0 portions in the patch - did you > send the correct version? 'fraid so. Sorry, I'd forgotten about that bit. Long story (not so) short, this patch is a bit of a frankenstein monster: there's a large portion from

Re: [PATCH] RISC-V: Add function multiversioning support

Could you add testcases? Also, could you splitted that into smaller patches to make it easier to review? On Sun, Oct 20, 2024 at 1:24 PM Yangyu Chen wrote: > > This patch adds support for function multi-versioning to the RISC-V > using the target_clones and target_versions attributes, which follo

Re: [PATCH] target: Fix asm codegen for vfpclasss* and vcvtph2* instructions

On Sat, Oct 19, 2024 at 2:06 AM Antoni Boucher wrote: > > Thanks for the review. > Here's the updated patch. > > Le 2024-10-17 à 21 h 50, Hongtao Liu a écrit : > > On Fri, Oct 18, 2024 at 9:08 AM Antoni Boucher wrote: > >> > >> Hi. > >> This is a patch for the bug 116725. > >> I'm not sure if it

[PATCH] simplify-rtx: Handle `a != 0 ? -a : 0` [PR58195]

The gimple (and generic) levels have this optmization since r12-2041-g7d6979197274a662da7bdc5. It seems like a good idea to add a similar one to rtl just in case it is not caught at the gimple level. Note the loop case in csel-neg-1.c is not handled at the gimple level (even with phiopt turned

Re: [patch, fortran] PR28032 gfortran.dg tests use dg-options with -On even though it is already torture tests

On 10/20/24 1:16 PM, Harald Anlauf wrote: Hi Jerry! Am 20.10.24 um 21:53 schrieb Jerry D: On 10/20/24 12:23 PM, Harald Anlauf wrote: Hi Jerry! Am 20.10.24 um 18:56 schrieb Jerry D: The attached diff file begins some test suite cleanup. The patch removes extra spaces between dg-do and the ru

Re: [PATCH v2] Introduce TARGET_CLONES_ATTR_SEPARATOR for RISC-V

Squashed to this: https://patchwork.sourceware.org/project/gcc/patch/tencent_3b2442361b6df87e046fb4e71d55715d6...@qq.com/ > On Oct 16, 2024, at 02:16, Yangyu Chen wrote: > > Some architectures may use ',' in the attribute string, but it is not > used as the separator for different targets. To a

[PATCH] RISC-V: Add function multiversioning support

This patch adds support for function multi-versioning to the RISC-V using the target_clones and target_versions attributes, which follow the RISC-V C-API Docs [1] and the existing proposal about priority syntax [2]. This patch copies many codes from commit 0cfde688e213 ("[aarch64] Add function mul

[PATCH 3/4] sched1: model: only promote true dependecies in predecessor promotion

Background -- sched1 runs a preliminary "model schedular" ahead of the main list schedular. Its sole purpose is to keep register pressure to mimimum [1] and it uses DFA register depenendency tracking to arrange insns. [1] https://gcc.gnu.org/legacy-ml/gcc-patches/2011-12/msg01684.html

Re: [patch, fortran] PR28032 gfortran.dg tests use dg-options with -On even though it is already torture tests

Hi Jerry! Am 20.10.24 um 21:53 schrieb Jerry D: On 10/20/24 12:23 PM, Harald Anlauf wrote: Hi Jerry! Am 20.10.24 um 18:56 schrieb Jerry D: The attached diff file begins some test suite cleanup. The patch removes extra spaces between dg-do and the run directive, I only have gone through gfort

Re: [patch, fortran] PR28032 gfortran.dg tests use dg-options with -On even though it is already torture tests

On 10/20/24 12:23 PM, Harald Anlauf wrote: Hi Jerry! Am 20.10.24 um 18:56 schrieb Jerry D: The attached diff file begins some test suite cleanup. The patch removes extra spaces between dg-do and the run directive, I only have gone through gfortran.dg and not its sub-directories. Interestingl

[PATCH 4/4] sched1: model: ICE on infinite loops in predecessor promotion (Not for Merge)

This is just a testing hack in case someone runs into infinite loops with model schedule change. I did run into quite a few during the course of development and instead of sched trace files eating up the disk, better to ICE and abort. gcc/ChangeLog: * haifa-sched.cc (model_promote_predece

[PATCH 2/4] RISC-V: Implement TARGET_SCHED_PRESSURE_PREFER_NARROW [PR/114729]

This inhibits sched1 aggressive spilling on RISC-V (see prev commit for details of what the hook does). On RISC-V (BPI-F3) we see good results. (Build: -Ofast -march=rv64gcv_zba_zbb_zbs) Before: -- Performance counter stats for './cactusBSSN_r_base.rivos spec_ref.par': 4,769,844.

[PATCH 1/4] sched1: hookize pressure scheduling spilling agressiveness

Pressure senstive scheduling seems to prefer "wide" schedules with more parallelism tending to more spills. This works better for in-order cores [1][2]. The Excess Change Cost (ECC) of an insn, essentially a proxy of register pressure attributed to an insn, deliberately ignores negative values (Pr

[PATCH 0/4] sched1 improvements

Hi, PFA patch series which improves sched1 spilling. This all started with SPEC2017 507.Cactu dynamic icounts on RISC-V being double than those of aarch64 (~2.6 trillion vs. ~1.4 trillion). Robin/Jeff hinted that the issue could be sched1 which it turned out to be. Essentially there are 2 fixes

Re: [patch, fortran] PR28032 gfortran.dg tests use dg-options with -On even though it is already torture tests

Hi Jerry! Am 20.10.24 um 18:56 schrieb Jerry D: The attached diff file begins some test suite cleanup. The patch removes extra spaces between dg-do and the run directive, I only have gone through gfortran.dg and not its sub-directories. Interestingly, one of the tests fails when this space is

[PATCH] phiopt: factor could move a trapping statement across other trapping statements [PR117235]

After r15-4503-g8d6d6d537fdc75, phiopt could move a trapping statement across another trapping statement causing the order to be incorrect (might happen with non-call exceptions). To prevent this, a trapping statement has to be at the end of the basic block to be allowed to be factored. This adds

[patch, fortran] PR28032 gfortran.dg tests use dg-options with -On even though it is already torture tests

The attached diff file begins some test suite cleanup. The patch removes extra spaces between dg-do and the run directive, I only have gone through gfortran.dg and not its sub-directories. Interestingly, one of the tests fails when this space is removed. I fixed that by adding in a -O in the d

Re: [PATCH 7/7] RISC-V: Disable by pieces for vector setmem length > UNITS_PER_WORD

On 10/19/24 7:09 AM, Jeff Law wrote: On 10/18/24 7:13 AM, Craig Blackmore wrote: For fast unaligned access targets, by pieces uses up to UNITS_PER_WORD size pieces resulting in more store instructions than needed.  For example gcc.target/riscv/rvv/base/setmem-1.c:f1 built with `-O3 -march=r

[PATCH] testsuite: arm: Use effective-target for attr-neon* tests

Ok for trunk and releases/gcc-14? -- The tests assume that a neon fpu is avialable and fails it not, so explicitly require it. gcc/testsuite/ChangeLog: * gcc.target/arm/attr-neon-builtin-fail.c: Use effective-target arm_neon. * gcc.target/arm/attr-neon-builtin-fail2.c: L

[PATCH] testsuite: arm: Relax expected asm in bitfield* and union-2 tests

Ok for trunk and releases/gcc-14? -- Below -O2, lsls/lsrs are prefered. For -O2 and above, lsl/lsr are prefered. gcc/testsuite/ChangeLog: * gcc.target/arm/cmse/mainline/8_1m/bitfield-4.c: Allow lsl and lsr instructions. * gcc.target/arm/cmse/mainline/8_1m/bitfield-6.c: L

[PATCH] testsuite: arm: Use check-function-bodies in fp16-aapcs-* tests

Ok for trunk and releases/gcc-14? -- Converted the tests to use check-function-bodies in order to ensure that the sequence is correct. gcc/testsuite/ChangeLog: * gcc.target/arm/fp16-aapcs-1.c: Use check-function-bodies. * gcc.target/arm/fp16-aapcs-2.c: Likewise. * gcc.ta

[PATCH] testsuite: arm: Use check-function-bodies in cmse-5 tests

Ok for trunk and releases/gcc-14? -- Converted the tests to use check-function-bodies in order to ensure that the sequence is correct. This also allows both APSR_nzcvq and APSR_nzcvqg as target selector does not work when the -march and/or -mcpu overrides the target to test. gcc/testsuite/Change

[PATCH] testsuite: Fix typo in ext-floating19.C

gcc/testsuite/ChangeLog: * g++.dg/cpp23/ext-floating19.C: Fix typo for bfloat16 guard. --- Ok for mainline? gcc/testsuite/g++.dg/cpp23/ext-floating19.C | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/testsuite/g++.dg/cpp23/ext-floating19.C b/gcc/testsuite/g++.dg

[PATCH] testsuite: add testcase for fixed PR115933

gcc/testsuite/ChangeLog: PR rtl-optimization/115933 * gcc.dg/pr115933.c: New test. --- The PR is fixed but the bisect wasn't conclusive (only to a range) and the testcase is sufficiently different from the commits in that range to be worth adding IMO. OK? gcc/testsuite/gcc.dg/pr1