From: xuli <xu...@eswincomputing.com> form 1: T __attribute__((noinline)) \ sat_u_sub_imm##IMM##_##T##_fmt_1 (T y) \ { \ return (T)IMM >= y ? (T)IMM - y : 0; \ }
Passed the rv64gcv regression test. gcc/testsuite/ChangeLog: * gcc.target/riscv/sat_u_sub_imm-1_3.c: New test. * gcc.target/riscv/sat_u_sub_imm-2_3.c: New test. * gcc.target/riscv/sat_u_sub_imm-3_3.c: New test. * gcc.target/riscv/sat_u_sub_imm-4_1.c: New test. Change-Id: I3e31b4f2294f6b5da8f52fa6f722126f3b245915 --- .../gcc.target/riscv/sat_u_sub_imm-1_3.c | 21 ++++++++++++++++ .../gcc.target/riscv/sat_u_sub_imm-2_3.c | 23 +++++++++++++++++ .../gcc.target/riscv/sat_u_sub_imm-3_3.c | 25 +++++++++++++++++++ .../gcc.target/riscv/sat_u_sub_imm-4_1.c | 20 +++++++++++++++ 4 files changed, 89 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-1_3.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-2_3.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-3_3.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-4_1.c diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-1_3.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-1_3.c new file mode 100644 index 00000000000..0291bfc3eb2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-1_3.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-flto" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "sat_arith.h" + +/* +** sat_u_sub_imm254_uint8_t_fmt_1: +** li\s+[atx][0-9]+,\s*254 +** sub\s+[atx][0-9]+,\s*[atx][0-9]+,\s*a0 +** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ +** addi\s+a0,\s*a0,\s*-1 +** and\s+a0,\s*a0,\s*[atx][0-9]+ +** andi\s+a0,\s*a0,\s*0xff +** ret +*/ + +DEF_SAT_U_SUB_IMM_FMT_1(uint8_t, 254) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-2_3.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-2_3.c new file mode 100644 index 00000000000..a87c0f8a03f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-2_3.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-flto" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "sat_arith.h" + +/* +** sat_u_sub_imm65534_uint16_t_fmt_1: +** li\s+[atx][0-9]+,\s*65536 +** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-2 +** sub\s+[atx][0-9]+,\s*[atx][0-9]+,\s*a0 +** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ +** addi\s+a0,\s*a0,\s*-1 +** and\s+a0,\s*a0,\s*[atx][0-9]+ +** slli\s+a0,\s*a0,\s*48 +** srli\s+a0,\s*a0,\s*48 +** ret +*/ + +DEF_SAT_U_SUB_IMM_FMT_1(uint16_t, 65534) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-3_3.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-3_3.c new file mode 100644 index 00000000000..3a7ff134a9a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-3_3.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-flto" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "sat_arith.h" + +/* +** sat_u_sub_imm4294967294_uint32_t_fmt_1: +** li\s+[atx][0-9]+,\s*1 +** slli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 +** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-2 +** slli\s+a0,\s*a0,\s*32 +** srli\s+a0,\s*a0,\s*32 +** sub\s+[atx][0-9]+,\s*[atx][0-9]+,\s*a0 +** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ +** addi\s+a0,\s*a0,\s*-1 +** and\s+a0,\s*a0,\s*[atx][0-9]+ +** sext\.w\s+a0,\s*a0 +** ret +*/ + +DEF_SAT_U_SUB_IMM_FMT_1(uint32_t, 4294967294) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-4_1.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-4_1.c new file mode 100644 index 00000000000..98b926c3313 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-4_1.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-flto" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "sat_arith.h" + +/* +** sat_u_sub_imm18446744073709551614u_uint64_t_fmt_1: +** li\s+[atx][0-9]+,\s*-2 +** sub\s+[atx][0-9]+,\s*[atx][0-9]+,\s*a0 +** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ +** addi\s+a0,\s*a0,\s*-1 +** and\s+a0,\s*a0,\s*[atx][0-9]+ +** ret +*/ + +DEF_SAT_U_SUB_IMM_FMT_1(uint64_t, 18446744073709551614u) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */ -- 2.17.1