[PATCH 4/8] i386: Support vectorized BF16 add/sub/mul/div with AVX10.2 instructions

From: Levy Hsu AVX10.2 introduces several non-exception instructions for BF16 vector. Enable vectorized BF add/sub/mul/div operation by supporting standard optab for them. gcc/ChangeLog: * config/i386/sse.md (div3): New expander for BFmode div. (VF_BHSD): New mode iterator with

[PATCH 8/8] i386: Support vec_cmp for V8BF/V16BF/V32BF in AVX10.2

From: Levy Hsu gcc/ChangeLog: * config/i386/i386-expand.cc (ix86_use_mask_cmp_p): Add BFmode for int mask cmp. * config/i386/sse.md (vec_cmp): New vec_cmp expand for VBF modes. gcc/testsuite/ChangeLog: * gcc.target/i386/avx10_2-512-bf-vector-cmpp-1.c:

[PATCH 6/8] i386: Support vectorized BF16 smaxmin with AVX10.2 instructions

From: Levy Hsu gcc/ChangeLog: * config/i386/sse.md (3): New define expand pattern for BF smaxmin. gcc/testsuite/ChangeLog: * gcc.target/i386/avx10_2-512-bf-vector-smaxmin-1.c: New test. * gcc.target/i386/avx10_2-bf-vector-smaxmin-1.c: New test. --- gcc/config/i3

[PATCH 3/8] i386: Optimize generate insn for avx10.2 compare

From: "Hu, Lin1" gcc/ChangeLog: * config/i386/i386-expand.cc (ix86_expand_fp_compare): Add UNSPEC to support the optimization. * config/i386/i386.cc (ix86_fp_compare_code_to_integer): Add NE/EQ. * config/i386/i386.md (*cmpx): New define_insn. (*cmpxhf): Di

[PATCH 7/8] i386: Support vectorized BF16 sqrt with AVX10.2 instruction

From: Levy Hsu gcc/ChangeLog: * config/i386/sse.md: Expand VF2H to VF2HB with VBF modes. --- gcc/config/i386/sse.md | 13 - 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index b374783429c..2de592a9c8f 100644 ---

[PATCH 5/8] i386: Support vectorized BF16 FMA with AVX10.2 instructions

From: Levy Hsu gcc/ChangeLog: * config/i386/sse.md: Add V8BF/V16BF/V32BF to mode iterator FMAMODEM. gcc/testsuite/ChangeLog: * gcc.target/i386/avx10_2-512-bf-vector-fma-1.c: New test. * gcc.target/i386/avx10_2-bf-vector-fma-1.c: New test. --- gcc/config/i386/sse.md

[PATCH 0/8] i386: Opmitize code with AVX10.2 new instructions

Hi all, I have just commited AVX10.2 new instructions patches into trunk hours ago. The next and final part for AVX10.2 upstream is to optimize code with AVX10.2 new instructions. In this patch series, it will contain the following optimizations: - VNNI instruction auto vectorize (PATCH 1).

[PATCH 2/8] i386: Optimize ordered and nonequal

From: "Hu, Lin1" Currently, when we input !__builtin_isunordered (a, b) && (a != b), gcc will emit ucomiss %xmm1, %xmm0 movl $1, %ecx setp %dl setnp %al cmovne %ecx, %edx andl %edx, %eax movzbl %al, %eax In fact, xorl %eax, %eax ucomiss %xmm1, %xmm0 setne %al is better. gcc/

[PATCH 1/8] i386: Auto vectorize sdot_prod, usdot_prod, udot_prod with AVX10.2 instructions

gcc/ChangeLog: * config/i386/sse.md (VI1_AVX512VNNIBW): New. (VI2_AVX10_2): Ditto. (sdot_prod): Add AVX10.2 to auto vectorize and combine 512 bit part. (udot_prod): Ditto. (sdot_prodv64qi): Removed. (udot_prodv64qi): Ditto. (usdot_pro

Re: [PATCH] tree-optimization/116166 - forward jump-threading going wild

[I'm slowly coming up to speed here after my absence, so please bear with me...] I suspect there's a few things going on here, both in the forward and the backwards threader. For the forward threader, you mention some very good points in the PR. First, there's unnecessary recursion in simplify_c

Re: [PATCH V2] rs6000: add clober and guard for vsx_stxvd2x4_le_const[pr116030]

Hi Jeff, I just noticed this v2 ... on 2024/8/22 14:22, Jiufu Guo wrote: > Hi, > > Previous, vsx_stxvd2x4_le_const_ is introduced for 'split1' pass, > so it is guarded by "can_create_pseudo_p ()". > While, it would be possible to match the pattern of this insn during/after > RA, so this insn cou

Re: [PATCH] rs6000: allow split vsx_stxvd2x4_le_const after RA[pr116030]

Hi, on 2024/8/21 15:23, Jiufu Guo wrote: > Hi, > > Previous, vsx_stxvd2x4_le_const_ is introduced for 'split1' pass, > so it is guarded by "can_create_pseudo_p ()". > While, it would be possible to match the pattern of this insn during/after > RA, so this insn could be updated to make it work for

Re: [PATCH ver 3] rs6000,extend and document built-ins vec_test_lsbb_all_ones and vec_test_lsbb_all_zeros

Hi Carl, on 2024/8/22 23:24, Carl Love wrote: > Gcc maintainers: > > Version 3, fixed a few typos per Kewen's review.  Fixed the expected number > of scan-assembler-times for xvtlsbb and setbc.  Retested on Power 10 LE. > > Version 2, based on discussion additional overloaded instances of the

Re: [PATCH] sched: Don't skip empty block by removing no_real_insns_p [PR108273]

Hi Jeff, on 2024/8/26 06:13, Jeff Law wrote: > > So is this patch still relevant Kewen? Yes, sorry that I forgot to follow up this after stage 1 opens. > > On 12/20/23 2:25 AM, Kewen.Lin wrote: >> Hi, >> >> This patch follows Richi's suggestion "scheduling shouldn't >> special case empty block

[PATCH] Fix bootstap-errors due to enabling -gvariable-location-views

This recent change triggered various bootsteap-errors, mostly on x86 targets because line info advance address entries were output in the wrong section table. The switch to the wrong line table happened in dwarfout_set_ignored_loc. It must use the same section as the earlier called dwarf2out_switch

RE: [PATCH v3] RISC-V: Support IMM for operand 0 of ussub pattern

Got it, thanks Jeff. Pan -Original Message- From: Jeff Law Sent: Monday, August 26, 2024 10:21 AM To: Li, Pan2 ; gcc-patches@gcc.gnu.org Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; rdapp@gmail.com Subject: Re: [PATCH v3] RISC-V: Support IMM for operand 0 of ussub pattern On 8

Re: [PATCH v3] RISC-V: Support IMM for operand 0 of ussub pattern

On 8/25/24 7:35 PM, Li, Pan2 wrote: Thanks Jeff. OK. I'm assuming we don't have to worry about the case where X is wider than Xmode? ie, a DImode on rv32? Yes, the DImode is disabled by ANYI iterator for ussub pattern. Thanks. Just wanted to make sure. And for the avoidance of doubt, t

[PATCH v3] Match: Support form 1 for scalar signed integer .SAT_ADD

From: Pan Li This patch would like to support the form 1 of the scalar signed integer .SAT_ADD. Aka below example: Form 1: #define DEF_SAT_S_ADD_FMT_1(T, UT, MIN, MAX) \ T __attribute__((noinline)) \ sat_s_add_##T##_fmt_1 (T x, T y) \ {

Re: [PATCH] RISC-V: Bugfix for Duplicate entries for -mtune in --target-help[Bug 116347]

在 2024/8/25 23:38, Jeff Law 写道: On 8/19/24 2:14 AM, shiyul...@iscas.ac.cn wrote: From: yulong This patch try to fix a bug[116347]. I change the name of the micro-arch, because I think micro-arch and core have the same name that caused the error. gcc/ChangeLog: * config/riscv/

Re: [PATCHv4, expand] Add const0 move checking for CLEAR_BY_PIECES optabs

On Fri, Aug 23, 2024 at 5:46 PM HAO CHEN GUI wrote: > > Hi Hongtao, > > 在 2024/8/23 11:47, Hongtao Liu 写道: > > On Fri, Aug 23, 2024 at 11:03 AM HAO CHEN GUI wrote: > >> > >> Hi Hongtao, > >> > >> 在 2024/8/23 9:47, Hongtao Liu 写道: > >>> On Thu, Aug 22, 2024 at 4:06 PM HAO CHEN GUI > >>> wrote: >

Re: [PATCH 00/12] AVX10.2: Support new instructions

On Mon, Aug 19, 2024 at 4:57 PM Haochen Jiang wrote: > > Hi all, > > The AVX10.2 ymm rounding patches has been merged to trunk around > 6 hours ago. As mentioned before, next step will be AVX10.2 new > instruction support. > > This patch series could be divided into three part. > > The first patch

RE: [PATCH v1] Vect: Promote unsigned .SAT_ADD constant operand for vectorizable_call

Thanks Richard for comments and confirmation. > Instead pattern recognition of .SAT_ADD should promote/demote the invariants - Got it, will have a try to reconcile the types in .SAT_ADD for const_int. > What I read is that > .ADD_OVERFLOW > produces a value that is equal to the twos-complement a

RE: [PATCH v3] RISC-V: Support IMM for operand 0 of ussub pattern

Thanks Jeff. > OK. I'm assuming we don't have to worry about the case where X is wider > than Xmode? ie, a DImode on rv32? Yes, the DImode is disabled by ANYI iterator for ussub pattern. Pan -Original Message- From: Jeff Law Sent: Sunday, August 25, 2024 11:22 PM To: Li, Pan2 ; gcc

Re: [committed] libstdc++: Make std::vector::reference constructor private [PR115098]

On Fri, Aug 23, 2024 at 5:20 AM Jonathan Wakely wrote: > > Tested x86_64-linux. Pushed to trunk. > > -- >8 -- > > The standard says this constructor should be private. LWG 4141 proposes > to remove it entirely. We still need it, but it doesn't need to be > public. > > For std::bitset the default

Re: [PATCH v2] RISC-V: More support of vx and vf for autovec comparison

On 7/19/24 2:54 AM, demin.han wrote: There are still some cases which can't utilize vx or vf after last_combine pass. 1. integer comparison when imm isn't in range of [-16, 15] 2. float imm is 0.0 3. DI or DF mode under RV32 This patch fix above mentioned issues. Tested on RV32 and RV64. S

Re: [RFC/RFA] [PATCH v2 09/12] Add symbolic execution support.

On 8/20/24 5:41 AM, Richard Biener wrote: So the store-merging variant IIRC tracks a single overall source only (unless it was extended and I missed that) and operates at a byte granularity. I did want to extend it to support vector shuffles at one point (with two sources then), but didn't

Re: [PATCH v5 1/1] RISC-V: Add support for XCVbitmanip extension in CV32E40P

On 8/4/24 12:35 PM, Mary Bennett wrote: Spec: github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md Contributors: Mary Bennett Nandni Jamnadas Pietra Ferreira Charlie Keaney Jessica Mills Craig Blackmore Simon Cook Jeremy Bennett H

Re: [PATCH] ifcvt: Clarify if_info.original_cost.

I think Manolis's patches are all in, time to revisit this one? On 6/12/24 1:54 AM, Robin Dapp wrote: Hmm, ok. The bit that confused me most was: if (last_needs_comparison != -1) { end_sequence (); start_sequence (); ... } which implied that the second at

Re: [PATCH] sched: Don't skip empty block by removing no_real_insns_p [PR108273]

So is this patch still relevant Kewen? On 12/20/23 2:25 AM, Kewen.Lin wrote: Hi, This patch follows Richi's suggestion "scheduling shouldn't special case empty blocks as they usually do not appear" in [1], it removes function no_real_insns_p and its uses completely. There is some case that o

Re: [PATCH] RISC-V: Fix double mode under RV32 not utilize vf

On Fri, Jul 19, 2024 at 12:07 PM Jeff Law wrote: > > > On 7/19/24 2:55 AM, demin.han wrote: > > Currently, some binops of vector vs double scalar under RV32 can't > > translated to vf but vfmv+vxx.vv. > > > > The cause is that vec_duplicate is also expanded to broadcast for double > mode > > unde

[PATCH] expand: Use the correct mode for store flags for popcount [PR116480]

When expanding popcount used for equal to 1 (or rather __builtin_stdc_has_single_bit), the wrong mode was bsing used for the mode of the store flags. We were using the mode of the argument to popcount but since popcount's return value is always int, the mode of the expansion here should have bee

[PATCH] vect: Fix STMT_VINFO_DEF_TYPE check for odd/even widen mult [PR116348]

After fixing PR116142 some code started to trigger an ICE with -O3 -march=znver4. Per Richard Biener who actually made this fix: "supportable_widening_operation fails at transform time - that's likely because vectorizable_reduction "puns" defs to internal_def" so the check should use STMT_VINFO_

[PATCH] libstdc++: Fix @file for target-specific opt_random.h

A few of these files self-identified as ext/random.tcc, update to use the actual basename. libstdc++-v3/ChangeLog: * config/cpu/aarch64/opt/ext/opt_random.h: Improve doxygen file docs. * config/cpu/i486/opt/ext/opt_random.h: Likewise. --- libstdc++-v3/config/cpu/aarch64/o

[PATCH] libstdc++: Fix @headername for bits/cpp_typetraits.h

There is no file ext/type_traits, point it to ext/type_traits.h instead. libstdc++-v3/ChangeLog: * include/bits/cpp_type_traits.h: Improve doxygen file docs. --- libstdc++-v3/include/bits/cpp_type_traits.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libstdc++-v3/i

Re: [RFC/RFA][PATCH v2 01/12] Implement internal functions for efficient CRC computation

On 7/26/24 12:05 PM, Mariam Arutunian wrote:    Add two new internal functions (IFN_CRC, IFN_CRC_REV), to provide faster CRC generation.    One performs bit-forward and the other bit-reversed CRC computation.    If CRC optabs are supported, they are used for the CRC computation.    Otherw

Re: [RFC/RFA][PATCH v2 02/12] Add built-ins and tests for bit-forward and bit-reversed CRCs

On 7/26/24 12:05 PM, Mariam Arutunian wrote:    This patch introduces new built-in functions to GCC for computing bit-forward and bit-reversed CRCs.    These builtins aim to provide efficient CRC calculation capabilities.    When the target architecture supports CRC operations (as indicate

Re: [RFC/RFA][PATCH v2 03/12] RISC-V: Add CRC expander to generate faster CRC.

On 7/26/24 12:06 PM, Mariam Arutunian wrote:   If the target is ZBC or ZBKC, it uses clmul instruction for the CRC calculation. Otherwise, if the target is ZBKB, generates table-based CRC, but for reversing inputs and the output uses bswap and brev8 instructions.   Add new tests to check C

Re: [RFC/RFA][PATCH v2 12/12] Add tests for CRC detection and generation.

On 7/26/24 12:07 PM, Mariam Arutunian wrote:    gcc/testsuite/gcc.dg/torture/        * crc-(1-29).c: New tests.        * crc-CCIT-data16-xorOutside_InsideFor.c: Likewise.        * crc-CCIT-data16.c: Likewise.        * crc-CCIT-data8.c: Likewise.        * crc-coremark16-data16.c: Likewis

Re: [PATCH] Re-add calling emit_clobber in lower-subreg.cc's resolve_simple_move.

On 8/12/24 10:12 AM, Xianmiao Qu wrote: The previous patch: https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=d8a6945c6ea22efa4d5e42fe1922d2b27953c8cd aimed to eliminate redundant MOV instructions by removing calling emit_clobber in lower-subreg.cc's resolve_simple_move. First, I found that anoth

Re: [PATCH] Re-add calling emit_clobber in lower-subreg.cc's resolve_simple_move.

On 8/14/24 10:20 AM, Xianmiao Qu wrote: As I described in the commit message, the absence of clobber could potentially lead to the register's lifetime occupying the entire function, according to the algorithm of the 'df_lr_bb_local_compute' function. And avoiding unnecessary liveness has alw

[PING^2] [PATCH] Add a bootstrap-native build config

Andi Kleen writes: PING^2 for the patch. (not sure if there is any maintainer to cc here, this is generic build infrastructure) > Andi Kleen writes: > > I wanted to ping this patch: > > https://gcc.gnu.org/pipermail/gcc-patches/2024-July/658729.html > > >> From: Andi Kleen >> >> ... that use

Re: [PING^2] [PATCH] PR116080: Fix test suite checks for musttail

Andi Kleen writes: PING^2 for https://gcc.gnu.org/pipermail/gcc-patches/2024-July/658602.html This fixes some musttail related test suite failures that cause noise on various targets. > Andi Kleen writes: > > I wanted to ping this patch. It fixes test suite noise on various > targets. > > http

Re: [PATCH v2] RISC-V: Add --with-cmodel configure option

On 8/4/24 8:24 PM, Hau Hsu wrote: Oh the Palmer's patch is here [PATCH] RISC-V: Add --with-cmodel configure-time argument gcc.gnu.org/pipermail/gcc-patches/2023-December/641172.html> gcc.gnu.org favicon.ico

Re: [PATCH] c++: Fix overeager Woverloaded-virtual with conversion operators [PR109918]

Hi Jason, On 24 Aug 2024, at 23:59, Simon Martin wrote: > Hi Jason, > > On 24 Aug 2024, at 15:13, Jason Merrill wrote: > >> On 8/23/24 12:44 PM, Simon Martin wrote: >>> We currently emit an incorrect -Woverloaded-virtual warning upon the >>> following >>> test case >>> >>> === cut here === >>> s

Re: [PATCH 8/9] RISC-V: Move helper functions above expand_const_vector

On 8/22/24 1:46 PM, Patrick O'Neill wrote: These subroutines will be used in expand_const_vector in a future patch. Relocate so expand_const_vector can use them. gcc/ChangeLog: * config/riscv/riscv-v.cc (expand_vector_init_insert_elems): Relocate. (expand_vector_init_trailing

Re: [PATCH 6/9] RISC-V: Emit costs for bool and stepped const vectors

On 8/22/24 1:46 PM, Patrick O'Neill wrote: These cases are handled in the expander (riscv-v.cc:expand_const_vector). We need the vector builder to detect these cases so extract that out into a new riscv-v.h header file. gcc/ChangeLog: * config/riscv/riscv-v.cc (class rvv_builder): Mo

Re: [PATCH 2/2] RISC-V: Constant synthesis by shifting the lower half

On 8/8/24 11:10 AM, Raphael Moreira Zinsly wrote: Improve handling of constants where the high half can be constructed by shifting the low half. gcc/ChangeLog: * config/riscv/riscv.cc (riscv_build_integer): Detect constants were the higher half is a shift of the lower half. g

Re: [patch,avr] Overhaul avr-ifelse RTL optimization pass

вс, 25 авг. 2024 г. в 17:55, Jeff Law : > > > On 8/23/24 6:20 AM, Richard Biener wrote: > > On Fri, Aug 23, 2024 at 2:16 PM Georg-Johann Lay wrote: > >> > >> This patch overhauls the avr-ifelse mini-pass that optimizes > >> two cbranch insns to one comparison and two branches. > >> > >> More opti

Re: [PATCH 2/2] RISC-V: Constant synthesis by shifting the lower half

On 8/8/24 11:10 AM, Raphael Moreira Zinsly wrote: Improve handling of constants where the high half can be constructed by shifting the low half. gcc/ChangeLog: * config/riscv/riscv.cc (riscv_build_integer): Detect constants were the higher half is a shift of the lower half. g

Re: ping: [PATCH] libcpp: Support extended characters for #pragma {push,pop}_macro [PR109704]

Hello- https://gcc.gnu.org/pipermail/gcc-patches/2024-January/642926.html Monthly ping for this one please :). Thanks... -Lewis On Sat, Jul 27, 2024 at 3:09 PM Lewis Hyatt wrote: > > Hello- > > https://gcc.gnu.org/pipermail/gcc-patches/2024-January/642926.html > > Ping please? Jakub + Jason, h

Re: [PATCH] RISC-V: Bugfix for Duplicate entries for -mtune in --target-help[Bug 116347]

On 8/19/24 2:14 AM, shiyul...@iscas.ac.cn wrote: From: yulong This patch try to fix a bug[116347]. I change the name of the micro-arch, because I think micro-arch and core have the same name that caused the error. gcc/ChangeLog: * config/riscv/riscv-cores.def (RISCV_TUNE): Rename.

Re: LRA: Fix setup_sp_offset

On Aug 25 2024, H.J. Lu wrote: > Is it because i386 pushes the return address on stack? Like m68k. -- Andreas Schwab, sch...@linux-m68k.org GPG Key fingerprint = 7578 EB47 D4E5 4D69 2510 2552 DF73 E780 A9DA AEC1 "And now for something completely different."

Re: [PATCH 1/4] Write CodeView information about enregistered optimized variables

On 8/18/24 7:15 PM, Mark Harmstone wrote: Enable variable tracking when outputting CodeView debug information, and make it so that we issue debug symbols for optimized variables in registers. This consists of S_LOCAL symbols, which give the name and the type of local variables, followed by S_D

Re: [PATCH v3] RISC-V: Support IMM for operand 0 of ussub pattern

On 8/18/24 11:23 PM, pan2...@intel.com wrote: From: Pan Li This patch would like to allow IMM for the operand 0 of ussub pattern. Aka .SAT_SUB(1023, y) as the below example. Form 1: #define DEF_SAT_U_SUB_IMM_FMT_1(T, IMM) \ T __attribute__((noinline)) \ sat_u_sub_imm##I

Re: [patch,avr] Overhaul avr-ifelse RTL optimization pass

On 8/23/24 6:16 AM, Georg-Johann Lay wrote: This patch overhauls the avr-ifelse mini-pass that optimizes two cbranch insns to one comparison and two branches. More optimization opportunities are realized, and the code has been refactored. No new regressions.  Ok for trunk? There is currentl

Re: LRA: Fix setup_sp_offset

On Sun, Aug 25, 2024 at 7:30 AM Jeff Law wrote: > > > > On 8/22/24 9:45 AM, Michael Matz wrote: > > This is part of making m68k work with LRA. See PR116429. > > In short: setup_sp_offset is internally inconsistent. It wants to > > setup the sp_offset for newly generated instructions. sp_offset

Re: [PATCH v2] combine.cc (make_more_copies): Copy attributes from the original pseudo, PR115883

On 8/21/24 8:48 AM, Hans-Peter Nilsson wrote: The only thing that's changed with the patch in v2 since the first version (pinged once) is the commit message. CC to the nexts-of-kin as a heads-up. Regtested cross to cris-elf and native x86_64-linux-gnu at r15-3043-g64028d626a50. The gcc.dg/g

Re: [PATCH] optabs-query: Guard smallest_int_mode_for_size [PR115495].

On 8/22/24 7:57 AM, Robin Dapp wrote: Indeed though that might be a larger change. I have tested the attached now, aarch64 is still running but x86 and power10 are bootstrapped and regtested, riscv regtested. Hope I didn't miss any target-specific code that I haven't tested. As the issue

Re: LRA: Fix setup_sp_offset

On 8/22/24 9:45 AM, Michael Matz wrote: This is part of making m68k work with LRA. See PR116429. In short: setup_sp_offset is internally inconsistent. It wants to setup the sp_offset for newly generated instructions. sp_offset for an instruction is always the state of the sp-offset right be

Re: LRA: Don't use 0 as initialization for sp_offset

On 8/22/24 9:44 AM, Michael Matz wrote: this is part of making m68k work with LRA. See PR116374. m68k has the property that sometimes the elimation offset between %sp and %argptr is zero. During setting up elimination infrastructure it's changes between sp_offset and previous_offset that fee

Re: [RFC] RISC-V: Add cost model asserts

On 8/22/24 1:50 PM, Patrick O'Neill wrote: Applies after the recent 9 patch series: "RISC-V: Improve const vector costing and expansion" https://inbox.sourceware.org/gcc-patches/20240822194705.2789364-1-patr...@rivosinc.com/T/#t This isn't functional due to RTX hash collisions. It was incredi

Re: [patch,avr] Overhaul avr-ifelse RTL optimization pass

On 8/23/24 6:20 AM, Richard Biener wrote: On Fri, Aug 23, 2024 at 2:16 PM Georg-Johann Lay wrote: This patch overhauls the avr-ifelse mini-pass that optimizes two cbranch insns to one comparison and two branches. More optimization opportunities are realized, and the code has been refactore

Re: [PATCH 4/9] RISC-V: Reorder insn cost match order to match corresponding expander match order

On 8/22/24 1:46 PM, Patrick O'Neill wrote: The corresponding expander (riscv-v.cc:expand_const_vector) matches const_vec_duplicate_p before const_vec_series_p. Reorder to match this behavior when calculating costs. gcc/ChangeLog: * config/riscv/riscv.cc (riscv_const_insns): Relocate.

Re: [PATCH] testsuite: Run array54.C only for sync_int_long targets

On 8/24/24 11:51 AM, Dimitar Dimitrov wrote: On Tue, Aug 06, 2024 at 10:16:36PM +0300, Dimitar Dimitrov wrote: The test case uses "atomic", which fails to link on pru-unknown-elf target due to missing __atomic_load_4 symbol. Fix by filtering for sync_int_long effective target. Ensured that

Re: [PATCH v1 1/2] RISC-V: Add testcases for unsigned scalar .SAT_TRUNC form 4

On 8/25/24 12:18 AM, pan2...@intel.com wrote: From: Pan Li This patch would like to add test cases for the unsigned scalar quad and oct .SAT_TRUNC form 4. Aka: Form 4: #define DEF_SAT_U_TRUNC_FMT_4(NT, WT) \ NT __attribute__((noinline)) \ sat_u_trunc_##W

[committed] Disable late-combine in another RISC-V test

Another test where the output was slightly twiddled by late-combine in which simply disabling late-combine seems to be the best option. Running /home/jlaw/test/gcc/gcc/testsuite/gcc.target/riscv/riscv.exp ... FAIL: gcc.target/riscv/cm_mv_rv32.c -Os check-function-bodies sum Pushing to th

[committed] Fix assembly scan for RISC-V VLS tests

Surya's IRA patch from June slightly improves the code we generate for the vls/calling-conventions tests on RISC-V. Specifically it removes an unnecessary move from the instruction stream. This (of course) broke those tests: Running /home/jlaw/test/gcc/gcc/testsuite/gcc.target/riscv/rvv/rv

[committed] Turn off late-combine for a few risc-v specific tests

Just minor testsuite adjustments -- several of the shorten-memref tests are slightly twiddled by the late-combine pass: Running /home/jlaw/test/gcc/gcc/testsuite/gcc.target/riscv/riscv.exp ... FAIL: gcc.target/riscv/shorten-memrefs-2.c -Os scan-assembler store1a:\n(\t?\\.[^\n]*\n)*\taddi

Re: [x86_64 PATCH] Update STV's gains for TImode arithmetic right shifts on AVX2.

V sob., 24. avg. 2024 17:11 je oseba Roger Sayle napisala: > > This patch tweaks timode_scalar_chain::compute_convert_gain to better > reflect the expansion of V1TImode arithmetic right shifts by the i386 > backend. The comment "see ix86_expand_v1ti_ashiftrt" appears after > "case ASHIFTRT" in c

Re: [PATCH v1] Vect: Promote unsigned .SAT_ADD constant operand for vectorizable_call

On Sat, Aug 24, 2024 at 1:31 PM Li, Pan2 wrote: > > Thanks Jakub and Richard for explanation and help, I will double check > saturate matching for the const_int strict check. > > Back to this below case, do we still need some ad-hoc step to unblock the > type check when vectorizable_call? > For

Re: [RFC/RFA][PATCH v4 06/12] aarch64: Implement new expander for efficient CRC computation

On Sat, Aug 24, 2024 at 9:22 AM Mariam Arutunian wrote: > > > > On Fri, Aug 23, 2024, 15:03 Richard Biener wrote: >> >> On Fri, Aug 23, 2024 at 9:55 AM Mariam Arutunian >> wrote: >> > >> > >> > On Wed, Aug 21, 2024 at 5:56 PM Richard Sandiford >> > wrote: >> >> >> >> Mariam Arutunian writes: