Surya's IRA patch from June slightly improves the code we generate for
the vls/calling-conventions tests on RISC-V. Specifically it removes an
unnecessary move from the instruction stream. This (of course) broke
those tests:
Running /home/jlaw/test/gcc/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp ...
FAIL: gcc.target/riscv/rvv/autovec/vls/calling-convention-1.c -O3
-ftree-vectorize -mrvv-vector-bits=scalable scan-assembler-times
mv\\s+s0,a0\\s+call\\s+memset\\s+mv\\s+a0,s0 3
FAIL: gcc.target/riscv/rvv/autovec/vls/calling-convention-2.c -O3
-ftree-vectorize -mrvv-vector-bits=scalable scan-assembler-times
mv\\s+s0,a0\\s+call\\s+memset\\s+mv\\s+a0,s0 3
FAIL: gcc.target/riscv/rvv/autovec/vls/calling-convention-3.c -O3
-ftree-vectorize -mrvv-vector-bits=scalable scan-assembler-times
mv\\s+s0,a0\\s+call\\s+memset\\s+mv\\s+a0,s0 3
FAIL: gcc.target/riscv/rvv/autovec/vls/calling-convention-4.c -O3
-ftree-vectorize -mrvv-vector-bits=scalable scan-assembler-times
mv\\s+s0,a0\\s+call\\s+memset\\s+mv\\s+a0,s0 3
FAIL: gcc.target/riscv/rvv/autovec/vls/calling-convention-5.c -O3
-ftree-vectorize -mrvv-vector-bits=scalable scan-assembler-times
mv\\s+s0,a0\\s+call\\s+memset\\s+mv\\s+a0,s0 3
FAIL: gcc.target/riscv/rvv/autovec/vls/calling-convention-6.c -O3
-ftree-vectorize -mrvv-vector-bits=scalable scan-assembler-times
mv\\s+s0,a0\\s+call\\s+memset\\s+mv\\s+a0,s0 3
FAIL: gcc.target/riscv/rvv/autovec/vls/calling-convention-7.c -O3
-ftree-vectorize -mrvv-vector-bits=scalable scan-assembler-times
mv\\s+s0,a0\\s+call\\s+memset\\s+mv\\s+a0,s0 3
This patch does the natural adjustment of those tests by dropping the
moves from the scan.
Pushing to the trunk.
Jeff
commit 4c3485897d3e28ecfbe911f21f83fa047ee8b54b
Author: Jeff Law <j...@ventanamicro.com>
Date: Sun Aug 25 07:16:50 2024 -0600
[committed] Fix assembly scan for RISC-V VLS tests
Surya's IRA patch from June slightly improves the code we generate for the
vls/calling-conventions tests on RISC-V. Specifically it removes an
unnecessary move from the instruction stream. This (of course) broke those
tests:
> Running /home/jlaw/test/gcc/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp ...
> FAIL: gcc.target/riscv/rvv/autovec/vls/calling-convention-1.c -O3
-ftree-vectorize -mrvv-vector-bits=scalable scan-assembler-times
mv\\s+s0,a0\\s+call\\s+memset\\s+mv\\s+a0,s0 3
> FAIL: gcc.target/riscv/rvv/autovec/vls/calling-convention-2.c -O3
-ftree-vectorize -mrvv-vector-bits=scalable scan-assembler-times
mv\\s+s0,a0\\s+call\\s+memset\\s+mv\\s+a0,s0 3
> FAIL: gcc.target/riscv/rvv/autovec/vls/calling-convention-3.c -O3
-ftree-vectorize -mrvv-vector-bits=scalable scan-assembler-times
mv\\s+s0,a0\\s+call\\s+memset\\s+mv\\s+a0,s0 3
> FAIL: gcc.target/riscv/rvv/autovec/vls/calling-convention-4.c -O3
-ftree-vectorize -mrvv-vector-bits=scalable scan-assembler-times
mv\\s+s0,a0\\s+call\\s+memset\\s+mv\\s+a0,s0 3
> FAIL: gcc.target/riscv/rvv/autovec/vls/calling-convention-5.c -O3
-ftree-vectorize -mrvv-vector-bits=scalable scan-assembler-times
mv\\s+s0,a0\\s+call\\s+memset\\s+mv\\s+a0,s0 3
> FAIL: gcc.target/riscv/rvv/autovec/vls/calling-convention-6.c -O3
-ftree-vectorize -mrvv-vector-bits=scalable scan-assembler-times
mv\\s+s0,a0\\s+call\\s+memset\\s+mv\\s+a0,s0 3
> FAIL: gcc.target/riscv/rvv/autovec/vls/calling-convention-7.c -O3
-ftree-vectorize -mrvv-vector-bits=scalable scan-assembler-times
mv\\s+s0,a0\\s+call\\s+memset\\s+mv\\s+a0,s0 3
This patch does the natural adjustment of those tests by dropping the moves
from the scan.
gcc/testsuite
* gcc.target/riscv/rvv/autovec/vls/calling-convention-1.c: Update
expected output.
* gcc.target/riscv/rvv/autovec/vls/calling-convention-2.c: Likewise.
* gcc.target/riscv/rvv/autovec/vls/calling-convention-3.c: Likewise.
* gcc.target/riscv/rvv/autovec/vls/calling-convention-4.c: Likewise.
* gcc.target/riscv/rvv/autovec/vls/calling-convention-5.c: Likewise.
* gcc.target/riscv/rvv/autovec/vls/calling-convention-6.c: Likewise.
* gcc.target/riscv/rvv/autovec/vls/calling-convention-7.c: Likewise.
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-1.c
index 60c838eb21d..82039f5ac4e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-1.c
@@ -145,7 +145,7 @@ DEF_RET1_ARG9 (v4096qi)
// RET1_ARG0 tests
/* { dg-final { scan-assembler-times {li\s+a[0-1],\s*0} 9 } } */
-/* { dg-final { scan-assembler-times {mv\s+s0,a0\s+call\s+memset\s+mv\s+a0,s0}
3 } } */
+/* { dg-final { scan-assembler-times {call\s+memset} 3 } } */
// v1qi tests: return value (lbu) and function prologue (sb)
// 1 lbu per test, argnum sb's when args > 1
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-2.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-2.c
index b9922a64332..af52b703986 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-2.c
@@ -135,7 +135,7 @@ DEF_RET1_ARG9 (v2048hi)
// RET1_ARG0 tests
/* { dg-final { scan-assembler-times {li\s+a[0-1],\s*0} 8 } } */
-/* { dg-final { scan-assembler-times {mv\s+s0,a0\s+call\s+memset\s+mv\s+a0,s0}
3 } } */
+/* { dg-final { scan-assembler-times {call\s+memset} 3 } } */
// v1hi tests: return value (lhu) and function prologue (sh)
// 1 lhu per test, argnum sh's when args > 1
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-3.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-3.c
index 989d45de254..01c5a1a1ba2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-3.c
@@ -125,7 +125,7 @@ DEF_RET1_ARG9 (v1024si)
// RET1_ARG0 tests
/* { dg-final { scan-assembler-times {li\s+a[0-1],\s*0} 7 } } */
-/* { dg-final { scan-assembler-times {mv\s+s0,a0\s+call\s+memset\s+mv\s+a0,s0}
3 } } */
+/* { dg-final { scan-assembler-times {call\s+memset} 3 } } */
// v1si tests: return value (lw) and function prologue (sw)
// 1 lw per test, argnum sw's when args > 1
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-4.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-4.c
index b8bb2932de8..2c01aa8c260 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-4.c
@@ -115,7 +115,7 @@ DEF_RET1_ARG9 (v512di)
// RET1_ARG0 tests
/* { dg-final { scan-assembler-times {li\s+a[0-1],\s*0} 6 } } */
-/* { dg-final { scan-assembler-times {mv\s+s0,a0\s+call\s+memset\s+mv\s+a0,s0}
3 } } */
+/* { dg-final { scan-assembler-times {call\s+memset} 3 } } */
// v1di and v2di tests: return value (ld) and function prologue (sd)
// - 1 ld per v1di and 2 ld per v2di with args > 1
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-5.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-5.c
index f0357d30aec..98d6d4a758a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-5.c
@@ -135,7 +135,7 @@ DEF_RET1_ARG9 (v2048hf)
// RET1_ARG0 tests
/* { dg-final { scan-assembler-times {li\s+a[0-1],\s*0} 8 } } */
-/* { dg-final { scan-assembler-times {mv\s+s0,a0\s+call\s+memset\s+mv\s+a0,s0}
3 } } */
+/* { dg-final { scan-assembler-times {call\s+memset} 3 } } */
// v1hf tests: return value (lhu) and function prologue (sh)
// 1 lhu per test, argnum sh's when args > 1
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-6.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-6.c
index edf6539b0f2..5f59f001969 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-6.c
@@ -125,7 +125,7 @@ DEF_RET1_ARG9 (v1024sf)
// RET1_ARG0 tests
/* { dg-final { scan-assembler-times {li\s+a[0-1],\s*0} 7 } } */
-/* { dg-final { scan-assembler-times {mv\s+s0,a0\s+call\s+memset\s+mv\s+a0,s0}
3 } } */
+/* { dg-final { scan-assembler-times {call\s+memset} 3 } } */
// v1sf tests: return value (lw) and function prologue (sw)
// 1 lw per test, argnum sw's when args > 1
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-7.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-7.c
index e001a73de52..1d427fd08d6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-7.c
@@ -115,7 +115,7 @@ DEF_RET1_ARG9 (v512df)
// RET1_ARG0 tests
/* { dg-final { scan-assembler-times {li\s+a[0-1],\s*0} 6 } } */
-/* { dg-final { scan-assembler-times {mv\s+s0,a0\s+call\s+memset\s+mv\s+a0,s0}
3 } } */
+/* { dg-final { scan-assembler-times {call\s+memset} 3 } } */
// v1df and v2df tests: return value (ld) and function prologue (sd)
// - 1 ld per v1df and 2 ld per v2df with args > 1
