Currently, if a warning references a cloned function, the name of the cloned
function will be emitted in the "In function 'xyz'" part of the diagnostic,
which users aren't supposed to see. This patch follows the DECL_ABSTRACT_ORIGIN
links until encountering the original function.
gcc/ChangeLog:
From: Pan Li
It seems that the asm check is incorrect for truncated after SAT_SUB,
we should take the vx check for vssubu instead of vv check.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-1.c:
Update vssubu check from vv to vx.
* gcc.
From: Pan Li
This patch would like to implement the simple .SAT_TRUNC pattern
in the riscv backend. Aka:
Form 1:
#define DEF_SAT_U_TRUC_FMT_1(NT, WT) \
NT __attribute__((noinline)) \
sat_u_truc_##WT##_to_##NT##_fmt_1 (WT x) \
{\
From: Pan Li
This patch would like to support the .SAT_TRUNC for the unsigned
vector int. Given we have below example code:
Form 1
#define VEC_DEF_SAT_U_TRUC_FMT_1(NT, WT) \
void __attribute__((noinline)) \
vec_sat_u_truc_#
On Wed, Jul 3, 2024 at 2:10 AM Andi Kleen wrote:
>
> liuhongt writes:
>
> > From: "H.J. Lu"
> >
> > According to Intel® 64 and IA-32 Architectures Optimization Reference
> > Manual[1], Branch Hint is updated for Redwood Cove.
> >
> > cut from [1]-
> > Starting wit
LGTM, BTW, based on the discussion[1], my understanding is: depend ==
require == imply for the RISC-V ISA spec.
[1] https://github.com/riscv/riscv-v-spec/issues/723#issuecomment-922153867
On Wed, Jul 3, 2024 at 9:21 AM Patrick O'Neill wrote:
> From: Palmer Dabbelt
>
> gcc/ChangeLog:
>
>
gcc/ChangeLog:
* doc/invoke.texi: Remove trailing whitespace.
Signed-off-by: Patrick O'Neill
---
gcc/doc/invoke.texi | 392 ++--
1 file changed, 196 insertions(+), 196 deletions(-)
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 68eb
Thanks Tamar.
Looks I missed the comments part, will update in v2.
Pan
-Original Message-
From: Tamar Christina
Sent: Tuesday, July 2, 2024 11:03 PM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; richard.guent...@gmail.com;
jeffreya...@gmail.com
From: Palmer Dabbelt
gcc/ChangeLog:
* doc/invoke.texi: Describe -march behavior for dependent extensions on
RISC-V.
---
Ok'd by Jeff Law here:
https://inbox.sourceware.org/gcc-patches/fae68675-519f-4d80-b0fb-dfd5d8a22...@gmail.com/
I'll let it sit on the lists overnight and comm
Thanks Jeff for comments.
> Rather than reference TARGET_64BIT, you should reference the new
> iterators names.
Got it, generated need some manual adjustment.
> You probably want gen_int_mode rather than GEN_INT.
Sure.
> Why are you using Pmode? Pmode is for pointers. This stuff looks
From: Gianluca Guida
The Zabha extension adds support for subword Zaamo ops.
Extension: https://github.com/riscv/riscv-zabha.git
Ratification: https://jira.riscv.org/browse/RVS-1685
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc
(riscv_subset_list::to_string): Skip zabha
On 6/25/24 4:06 PM, Patrick O'Neill wrote:
From: Gianluca Guida
The Zabha extension adds support for subword Zaamo ops.
Extension: https://github.com/riscv/riscv-zabha.git
Ratification: https://jira.riscv.org/browse/RVS-1685
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc
On 7/1/24 6:32 AM, Richard Sandiford wrote:
Thomas pointed out that we sometimes failed to eliminate some dead code
(specifically clobbers of otherwise unused registers) on nvptx when
late-combine is enabled. This happens because:
- combine is able to optimise the function in a way that expo
On 7/2/24 12:33 AM, pan2...@intel.com wrote:
The below tests suites are passed for this patch
1. The rv64gcv fully regression test.
2. The rv64gcv build with glibc
gcc/ChangeLog:
* config/riscv/iterators.md (TARGET_64BIT): Add new iterator
and related attr(s).
Rather than r
> Pengxuan Zheng writes:
> > This patch improves GCC’s vectorization of __builtin_popcount for
> > aarch64 target by adding popcount patterns for vector modes besides
> > QImode, i.e., HImode, SImode and DImode.
> >
> > With this patch, we now generate the following for V8HI:
> > cnt v1.16b,
Vectorconvert lowering was changed to use the convert optab directly
starting in r15-1677-gc320a7efcd35ba. I had filed an aarch64 specific
issue for this specific thing and it would make sense to add an aarch64
specific testcase instead of just having a x86_64 specific ones for
this.
Pushed as obv
On Tue, 2024-07-02 at 18:02 -0400, David Malcolm wrote:
> On Tue, 2024-07-02 at 16:17 +, Qing Zhao wrote:
[...snip...]
>
> > + path.add_event (cur_ch->condition, NULL_TREE, 0,
> > + "when the condition is evaluated to %s",
> > + cur_ch->is_true_path ? "t
On Tue, 2024-07-02 at 16:17 +, Qing Zhao wrote:
> due to code duplication from jump threading [PR109071]
> Control this with a new option -fdiagnostic-try-to-explain-harder.
The name -fdiagnostic-try-to-explain-harder seems a little too "cute"
to me, but I can't think of a better name.
Variou
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The patch is OK, thanks.
On Sat, Jun 29, 2024 at 03:10:43PM +0200, Alejandro Colomar wrote:
> Warn about the following:
>
> char s[3] = "foo";
>
> Initializing a char array with a string literal of the same length as
> the size of the array is usually a mistake. Rarely is the case where
>
Bootstrapped/regtested on x86_64-pc-linux-gnu, ok for trunk/branches?
-- >8 --
This extends the r11-5179 fix which doesn't work with multidimensional
arrays. In particular,
struct S {
explicit S() { }
};
auto p = new S[1][1]();
should not say "converting to S from initializer list wou
On 7/2/24 3:54 PM, Jakub Jelinek wrote:
Hi!
This C++26 paper allows structured bindings declaration in
if/while/for/switch conditions, where the structured binding shouldn't
be initialized by array (so in the standard only non-union class types;
as extension _Complex will also work and vectors w
On 7/2/24 3:54 PM, Jakub Jelinek wrote:
Hi!
The following patch implements the C++26 paper which makes delete
and delete[] on incomplete class types invalid, previously it has
been UB unless the class had trivial destructor and no custom
deallocator.
The patch uses permerror_opt, so -Wno-delete
On 7/2/24 3:54 PM, Jakub Jelinek wrote:
Hi!
C++26 is making in P2747R2 paper placement new constexpr.
While working on a patch for that, I've noticed we ICE starting with
GCC 14 on the following testcase.
The problem is that e.g. for the void * to sometype * casts checks,
we really assume the ca
Alex Coplan writes:
> On 02/07/2024 13:41, Richard Biener wrote:
>> On Tue, 2 Jul 2024, Alex Coplan wrote:
>>
>> > On 02/07/2024 10:46, Alex Coplan wrote:
>> > > On 02/07/2024 10:01, Richard Biener wrote:
>> > > > On Mon, 1 Jul 2024, Tamar Christina wrote:
>> > > >
>> > > > > > -Original Mes
Hi!
This C++26 paper allows structured bindings declaration in
if/while/for/switch conditions, where the structured binding shouldn't
be initialized by array (so in the standard only non-union class types;
as extension _Complex will also work and vectors will be diagnosed because
of conversion iss
Hi!
C++26 is making in P2747R2 paper placement new constexpr.
While working on a patch for that, I've noticed we ICE starting with
GCC 14 on the following testcase.
The problem is that e.g. for the void * to sometype * casts checks,
we really assume the casts have their operand constant evaluated
Hi!
The following patch implements the C++26 paper which makes delete
and delete[] on incomplete class types invalid, previously it has
been UB unless the class had trivial destructor and no custom
deallocator.
The patch uses permerror_opt, so -Wno-delete-incomplete makes it
still compile without
Pengxuan Zheng writes:
> This patch improves GCC’s vectorization of __builtin_popcount for aarch64
> target
> by adding popcount patterns for vector modes besides QImode, i.e., HImode,
> SImode and DImode.
>
> With this patch, we now generate the following for V8HI:
> cnt v1.16b, v0.16b
>
Dear all,
the attached patch addresses an effectively bogus warning about
uninitialized temporary string lengths of associate selectors.
The primary reason is that the array descriptor for a character
array is created before the corresponding string length is set.
Moving the setting of the string
[ Actually attaching the patch this time... ]
The pre-commit testing showed that making ext-dce only active at -O2 and
above would require minor edits to the tests. In some cases we had
specified -O1 in the test or specified no optimization level at all.
Those need to be bumped to -O2. In o
The pre-commit testing showed that making ext-dce only active at -O2 and
above would require minor edits to the tests. In some cases we had
specified -O1 in the test or specified no optimization level at all.
Those need to be bumped to -O2. In one test we had one set of
dg-options overriding
I was not aware of the requirement to regenerate the opt urls files
when adding a new option until the autobuilder complained.
Regenerate common.opt.urls for the -gprune-btf option added in:
b8977d928a7a btf: add -gprune-btf option
Pushed as obvious.
gcc/
* common.opt.urls: Regenerate.
liuhongt writes:
> From: "H.J. Lu"
>
> According to Intel® 64 and IA-32 Architectures Optimization Reference
> Manual[1], Branch Hint is updated for Redwood Cove.
>
> cut from [1]-
> Starting with the Redwood Cove microarchitecture, if the predictor has
> no store
Hello,
Em ter, 2024-07-02 às 16:46 +0800, Kewen.Lin escreveu:
> Hi,
>
> Gentle ping this patch:
>
> https://gcc.gnu.org/pipermail/gcc-patches/2024-May/651025.html
>
I am testing this patch on our Userspace Livepatching product and we
found no issues so far.
Thanks,
Giuliano.
> BR,
> Kewen
>
due to code duplication from jump threading [PR109071]
Control this with a new option -fdiagnostic-try-to-explain-harder.
This patch has been tested with -fdiagnostic-try-to-expain-harder on by
default to bootstrap gcc and regression testing on both x86 and aarch64,
resolved all bootstrap issues a
This patch introduces two new expanders for the aarch64 backend,
dedicated to generate optimized code for CRC computations.
The new expanders are designed to leverage specific hardware capabilities
to achieve faster CRC calculations,
particularly using the crc32, crc32c and pmull instructions when
On 7/2/24 7:57 AM, Richard Biener wrote:
On Tue, Jul 2, 2024 at 3:52 PM Georg-Johann Lay wrote:
...just noticed that disabling -ftree-ter would also fix PR53049
where it moves a volatile asm across a library call.
As explained in the PR this only avoids the issue by accident (and
with the
Hi Pan,
Ah so this is doing the same code as in match_unsigned_saturation_trunc inside
the vectorizer?
Looks good to me but can't approve, could you however also place the same
comment
about what it's matching from match_unsigned_saturation_trunc into the vector
one?
Thanks,
Tamar
> -Orig
Hi Matthew,
I see you pushed this based on Sandra's feedback and Richard's approval
(which is fine).
As a practical note, instead of
* doc/tm.texi: Regenerated.
* target.def (function_attribute_inlinable_p,
unspec_may_trap_p): Update documentation.
I'd use
On Tue, Jul 2, 2024 at 3:52 PM Georg-Johann Lay wrote:
>
> ...just noticed that disabling -ftree-ter would also fix PR53049
> where it moves a volatile asm across a library call.
As explained in the PR this only avoids the issue by accident (and
with the other comment
I'm trying to make sure this
...just noticed that disabling -ftree-ter would also fix PR53049
where it moves a volatile asm across a library call.
Am 02.07.24 um 15:42 schrieb Georg-Johann Lay:
Hi Jeff,
This is a patch to get correct code out of 64-bit
loads from address-space __memx.
The AVR address-spaces may require t
Currently instructions vgm and vrepi are utilized only for constant
vectors where the element mode equals the element mode of the
corresponding instruction. This patch lifts this restriction by making
use of those instructions for constant vectors even if element modes
do not coincide. For exampl
On Tue, Jul 2, 2024 at 3:43 PM Georg-Johann Lay wrote:
>
> Hi Jeff,
>
> This is a patch to get correct code out of 64-bit
> loads from address-space __memx.
>
> The AVR address-spaces may require that move insns issue
> calls to library support functions, a fact that -ftree-ter
> doesn't account f
Although for instructions MVI and MVIY it does not make a difference
whether the immediate is interpreted as signed or unsigned, GAS expects
unsigned immediates for instruction format SI_URD.
gcc/ChangeLog:
* config/s390/vector.md (mov): Fix output template for
movv1qi.
---
Boots
Hi Jeff,
This is a patch to get correct code out of 64-bit
loads from address-space __memx.
The AVR address-spaces may require that move insns issue
calls to library support functions, a fact that -ftree-ter
doesn't account for. tree-ssa-ter.cc then replaces an
expression across such a library
On 02/07/2024 13:41, Richard Biener wrote:
> On Tue, 2 Jul 2024, Alex Coplan wrote:
>
> > On 02/07/2024 10:46, Alex Coplan wrote:
> > > On 02/07/2024 10:01, Richard Biener wrote:
> > > > On Mon, 1 Jul 2024, Tamar Christina wrote:
> > > >
> > > > > > -Original Message-
> > > > > > From: Ta
From: Pan Li
This patch would like to support the .SAT_TRUNC for the unsigned
vector int. Given we have below example code:
Form 1
#define VEC_DEF_SAT_U_TRUC_FMT_1(NT, WT) \
void __attribute__((noinline)) \
vec_sat_u_truc_#
From: Steve Baird
The compiler incorrectly accepts Some_Object'Unchecked_Access'Image.
gcc/ada/
* sem_attr.adb
(Analyze_Image_Attribute.Check_Image_Type): Check for
E_Access_Attribute_Type prefix type.
Tested on x86_64-pc-linux-gnu, committed on master.
---
gcc/ada/se
From: Eric Botcazou
This lifts the limitation of the original implementation whereby the first
operand of the concatenation needs to have a length known at compiled time
in order for the static allocation to be used.
gcc/ada/
* exp_ch4.adb (Expand_Concatenate): In the case where an oper
From: Steve Baird
In some cases, a use clause (or a use type clause) occurring within a
protected operation is incorrectly ignored.
gcc/ada/
* exp_ch9.adb
(Expand_N_Protected_Body): Declare new procedure
Unanalyze_Use_Clauses and call it before analyzing the newly
From: Justin Squirek
This patch modifies the experimental 'Size'Class feature such that objects of
mutably tagged types can be assigned qualified expressions featuring a
definite type (e.g. Mutable_Obj := Root_Child_T'(Root_T with others => <>)).
gcc/ada/
* sem_ch5.adb:
(Analyze
From: Ronan Desplanques
gcc/ada/
* sem_ch12.adb (Save_And_Reset): Fix value of low bound used to
reset table.
Tested on x86_64-pc-linux-gnu, committed on master.
---
gcc/ada/sem_ch12.adb | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/ada/sem_ch12.adb b
From: Steve Baird
If type T1 is is a tagged null record with a Put_Image aspect specification
and type T2 is a null extension of T1 (with no aspect specifications), then
evaluation of a T2'Image call should include a call to the specified procedure
(as opposed to yielding "(NULL RECORD)").
gcc/a
From: Bob Duff
GNAT crashes on an iterator with a filter inside an expression function
that is the completion of an earlier spec.
gcc/ada/
* freeze.adb (Freeze_Type_Refs): If Node is in N_Has_Etype,
check that it has had its Etype set, because this can be
called early fo
From: Yannick Moy
Pragma/aspect Extensions_Visible should be analyzed before any
pre/post contracts on a subprogram, as the legality of conversions
of formal parameters to classwide type depends on the value of
Extensions_Visible. Now fixed.
gcc/ada/
* contracts.adb (Analyze_Pragmas_In_
From: Eric Botcazou
... implement support for ordering comparisons of discrete array types.
This extends the Support_Composite_Compare_On_Target feature to ordering
comparisons of discrete array types as specified by RM 4.5.2(26/3), when
the component type is a byte (unsigned).
Implement suppor
From: Javier Miranda
When an array has several dimensions, and inner dimmensions are
initialized using Ada 2022 null array aggregates, the compiler
crashes or reports spurious errors computing the bounds of the
null array aggregates. This patch fixes the problem and adds
new warnings reported whe
From: Eric Botcazou
The problem is that the call to Convert_View made from Make_Init_Call does
nothing because the Etype is not set on the second argument.
gcc/ada/
* exp_ch7.adb (Convert_View): Add third parameter Typ and use it if
the second parameter does not have an Etype.
From: Eric Botcazou
gcc/ada/
* debug.adb (dJ): Add back as unused.
Tested on x86_64-pc-linux-gnu, committed on master.
---
gcc/ada/debug.adb | 1 +
1 file changed, 1 insertion(+)
diff --git a/gcc/ada/debug.adb b/gcc/ada/debug.adb
index f7fcd399769..3313c4a408f 100644
--- a/gcc/ada/de
From: Eric Botcazou
The problem is that the implementation of the No_Default_Initialization
restriction assumes that no type initialization routines are needed and,
therefore, builds a dummy version of them, which goes against their use
for box-initialized components in aggregates.
Therefore thi
This is a first step towards having a device table so we can add new devices
more easily. It'll also make it easier to remove the deprecated GCN3 bits.
The patch should not change the behaviour of anything.
gcc/ChangeLog:
* config/gcn/gcn-opts.h (TARGET_GLOBAL_ADDRSPACE): New.
(
On Tue, 2 Jul 2024, Jennifer Schmitz wrote:
> This patch adds a pattern in match.pd folding x/sqrt(x) to sqrt(x) for
> -funsafe-math-optimizations. Test cases were added for double, float, and
> long double.
>
> The patch was bootstrapped and regtested on aarch64-linux-gnu, no regression.
> Ok
This patch adds a pattern in match.pd folding x/sqrt(x) to sqrt(x) for
-funsafe-math-optimizations. Test cases were added for double, float, and long
double.
The patch was bootstrapped and regtested on aarch64-linux-gnu, no regression.
Ok for mainline?
Signed-off-by: Jennifer Schmitz
gcc/
On Tue, 2 Jul 2024, Alex Coplan wrote:
> On 02/07/2024 10:46, Alex Coplan wrote:
> > On 02/07/2024 10:01, Richard Biener wrote:
> > > On Mon, 1 Jul 2024, Tamar Christina wrote:
> > >
> > > > > -Original Message-
> > > > > From: Tamar Christina
> > > > > Sent: Monday, July 1, 2024 9:14 PM
On 02/07/2024 10:46, Alex Coplan wrote:
> On 02/07/2024 10:01, Richard Biener wrote:
> > On Mon, 1 Jul 2024, Tamar Christina wrote:
> >
> > > > -Original Message-
> > > > From: Tamar Christina
> > > > Sent: Monday, July 1, 2024 9:14 PM
> > > > To: gcc-patches@gcc.gnu.org
> > > > Cc: nd ;
Am 01.07.24 um 11:37 schrieb Alejandro Colomar:
gcc/ChangeLog:
* doc/invoke.texi: Document -fasm.
Signed-off-by: Alejandro Colomar
---
gcc/doc/invoke.texi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 30c
On 02/07/2024 10:01, Richard Biener wrote:
> On Mon, 1 Jul 2024, Tamar Christina wrote:
>
> > > -Original Message-
> > > From: Tamar Christina
> > > Sent: Monday, July 1, 2024 9:14 PM
> > > To: gcc-patches@gcc.gnu.org
> > > Cc: nd ; rguent...@suse.de; j...@ventanamicro.com
> > > Subject:
Hi Paul,
yes, please go ahead with the merge. To my astonishment, I had no conflicts
with your patch. Mine is addressing copy-in/(out) aka packing/unpacking of
derived-type to class-type arguments.
Thanks for the patch.
- Andre
On Tue, 2 Jul 2024 09:21:26 +0100
Paul Richard Thomas wrote:
> H
> PR target/115739
>
> gcc/ChangeLog:
>
> * config/sparc/vxworks.h (SPARC_LONG_DOUBLE_TYPE_SIZE): New define.
OK, thanks!
--
Eric Botcazou
Hi!
I've committed the following patch as obvious to wwwdocs.
diff --git a/htdocs/projects/cxx-status.html b/htdocs/projects/cxx-status.html
index 4401c87e..65c120a3 100644
--- a/htdocs/projects/cxx-status.html
+++ b/htdocs/projects/cxx-status.html
@@ -184,6 +184,31 @@
14
+
> Isn't it true in general that mismatched push/pop confuses a CPUs stack
> engine? Does the distance of the push/pop make any difference here
> or in general?
We are not sure about the impact for distance, but the PPX hint was
just a performance hint. As mentioned in the apx spec, the mismatched
Hi,
Gentle ping this patch:
https://gcc.gnu.org/pipermail/gcc-patches/2024-May/651025.html
BR,
Kewen
on 2024/5/8 13:49, Kewen.Lin wrote:
> Hi,
>
> As the discussion in PR112980, although the current
> implementation for -fpatchable-function-entry* conforms
> with the documentation (making N NO
Hello All:
This version of patch relaxes store fusion for more use cases.
Common infrastructure using generic code for pair mem fusion of different
targets.
rs6000 target specific code implement virtual functions defined by generic code.
Target specific code are added in rs6000-mem-fusion.cc.
When we determine overrun we have to consider VMAT_CONTIGUOUS_REVERSE
the same as VMAT_CONTIGUOUS.
Bootstrapped on x86_64-unknown-linux-gnu, testing in progress.
PR tree-optimization/115741
* tree-vect-stmts.cc (get_group_load_store_type): Also
handle VMAT_CONTIGUOUS_REVER
Hi Andre,
Thank you for the review.
> ...snip...
>
> I am confused here, because you are assigning to rhs. When that is
> correct, why
> is there no else assigning zero to the rhs->_len when arg1 is not
> unlimited?
'rhs_class_expr' is highly confusing and came from the original use of this
pa
On Tue, Jul 2, 2024 at 5:24 AM Hongyu Wang wrote:
>
> Hi,
>
> According to APX spec, the pushp/popp pairs should be matched,
> otherwise the PPX hint cannot take effect and cause performance loss.
>
> In the ix86_expand_epilogue, there are several optimizations that may
> cause the epilogue using
Modified and pushed to r15-1765.
在 2024/7/2 上午11:50, Xi Ruoyao 写道:
On Tue, 2024-07-02 at 11:22 +0800, Lulu Cheng wrote:
+static int
+loongarch_insn_cost (rtx_insn *insn, bool speed)
+{
+ rtx x = PATTERN (insn);
+ int cost = pattern_cost (x, speed);
+
+ /* On LA464, prevent movcf2fr and movfr
On Tue, Jul 2, 2024 at 4:54 AM liuhongt wrote:
>
> From: "H.J. Lu"
>
> According to Intel® 64 and IA-32 Architectures Optimization Reference
> Manual[1], Branch Hint is updated for Redwood Cove.
>
> cut from [1]-
> Starting with the Redwood Cove microarchitecture,
On Tue, Jul 2, 2024 at 10:11 AM Richard Biener
wrote:
>
> On Mon, Jul 1, 2024 at 11:48 PM Andrew Pinski
> wrote:
> >
> > While looking into the original folding code for cabs
> > (moved to match in r6-4111-gabcc43f5323869), I noticed that
> > `cabs(x+0i)` was optimized even without the need of s
Pushed to r15-1764.
在 2024/7/2 上午11:21, Lulu Cheng 写道:
After r15-1579, ADD and LD/ST pairs will be merged into LDX/STX.
Cause these two tests to fail. To guarantee that these two tests pass,
add the compilation option '-fno-late-combine-instructions'.
gcc/testsuite/ChangeLog:
* gcc.tar
On Mon, Jul 1, 2024 at 11:48 PM Andrew Pinski wrote:
>
> While looking into the original folding code for cabs
> (moved to match in r6-4111-gabcc43f5323869), I noticed that
> `cabs(x+0i)` was optimized even without the need of sqrt.
> I also noticed that now the code generation in this case
> will
On Mon, Jul 1, 2024 at 11:48 PM Andrew Pinski wrote:
>
> Expanding cabs in powcab might be too late as forwprop might
> recombine the load from a memory with the complex expr. Moving
> instead to complex lowering allows us to use directly the real/imag
> component from the loads instead. This allo
On Mon, Jul 1, 2024 at 11:48 PM Andrew Pinski wrote:
>
> Since cabs expansion was removed from this pass,
> it would be good to rename it.
OK
> Bootstrapped and tested on x86_64-linux-gnu
>
> gcc/ChangeLog:
>
> * passes.def (expand_pow): Renamed from expand_powcabs.
> * timevar.d
Hi Jeevitha,
on 2024/6/19 20:39, jeevitha wrote:
> Hi All,
>
> Updated the patch based on review comments. This patch passed bootstrap
> and regression testing on powerpc64le-linux with no regressions.
>
> PR110040 exposes an issue concerning moves from vector registers to GPRs.
> There are two
On Mon, Jul 1, 2024 at 11:47 PM Andrew Pinski wrote:
>
> This is just a small optimization for the case where the real and imag
> parts are the same when lowering complex addition/subtraction. We only
> need to do the addition once when the real and imag parts are the same (on
> both sides of the
On Mon, 1 Jul 2024, Tamar Christina wrote:
> > -Original Message-
> > From: Tamar Christina
> > Sent: Monday, July 1, 2024 9:14 PM
> > To: gcc-patches@gcc.gnu.org
> > Cc: nd ; rguent...@suse.de; j...@ventanamicro.com
> > Subject: [PATCH 1/2]middle-end: fix wide_int_constant_multiple_p whe
On Mon, 1 Jul 2024, Tamar Christina wrote:
> Hi All,
>
> The current implementation of constant_multiple_of is doing a more limited
> version of aff_combination_constant_multiple_p.
>
> The only non-debug usage of constant_multiple_of will proceed with the values
> as affine trees. There is sco
On Mon, 1 Jul 2024, Tamar Christina wrote:
> Hi All,
>
> wide_int_constant_multiple_p tries to check if for two tree expressions a and
> b
> that there is a multiplier which makes a == b * c.
>
> This code however seems to think that there's no c where a=0 and b=0 are equal
> which is of course
On Mon, 1 Jul 2024, Matthew Malcomson wrote:
> Ping plus some extra people on Cc since I wasn't sure who to ask for review.
> (Adding maintainers for `middle-end` plus Richard S).
>
> N.b. I'd update the cover-letter to also mention that no existing
> implementation of `function_attribute_inlinab
On Tue, 11 Jun 2024, Richard Biener wrote:
> When the operand is gimplified to an extract of a register or a
> register we have to disallow memory as we otherwise fail to
> gimplify it properly. Instead of
>
> __asm__("" : "=rm" __imag );
>
> we want
>
> __asm__("" : "=rm" D.2772);
> _1
Hi!
on 2024/7/2 04:28, Segher Boessenkool wrote:
> On Mon, Jul 01, 2024 at 04:36:44PM +0200, Richard Biener wrote:
>> On Mon, Jul 1, 2024 at 8:17 AM Kewen.Lin wrote:
>>> As PR115659 shows, assuming c = x CMP y, there are some
>>> folding chances for patterns r = c ? 0/z : z/-1:
>>> - For r = c
Hi Paul,
In
@@ -1335,19 +1340,49 @@ get_class_info_from_ss (stmtblock_t * pre, gfc_ss *ss,
tree *eltype) rhs_function = true;
}
}
+ else if (cntnr != NULL_TREE)
+{
+ tmp = gfc_class_vptr_get (rhs_class_expr);
+ gfc_add_modify (pre, tmp, fold_convert (TREE_TYPE (tmp),
+
on 2024/7/1 22:28, Richard Biener wrote:
> On Mon, Jul 1, 2024 at 8:16 AM Kewen.Lin wrote:
>>
>> Hi,
>>
>> As PR115659 shows, assuming c = x CMP y, there are some
>> folding chances for patterns r = c ? -1/z : z/0.
>>
>> For r = c ? -1 : z, it can be folded into:
>> - r = c | z (with ior_optab s
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