Re: [PATCH 1/2] match.pd: Support combine cond_len_op + vec_cond similar to cond_op

On Wed, Sep 20, 2023 at 6:10 AM Lehua Ding wrote: > > This patch adds combine cond_len_op and vec_cond to cond_len_op like > cond_op. > > gcc/ChangeLog: > > * gimple-match.h (gimple_match_op::gimple_match_op): > Add interfaces for more arguments. > (gimple_match_op::set_op)

Pushed: [PATCH v2] LoongArch: Define HAVE_AS_TLS to 0 if it's undefined [PR112299]

Pushed r14-5030. The subject and ChangeLog are updated to include the PR number. The code change is same as v1. On Mon, 2023-10-30 at 20:44 +0800, chenglulu wrote: > > 在 2023/10/30 下午8:26, Xi Ruoyao 写道: > > On Mon, 2023-10-30 at 19:50 +0800, chenglulu wrote: > > > 在 2023/10/30 下午7:42, Xi Ruoyao

[PATCH 3/4] [PATCH 3/3] Change internal intrin call for AVX512 intrins

gcc/ChangeLog: * config/i386/avx512bf16vlintrin.h (_mm_avx512_castsi128_ps): New. (_mm256_avx512_castsi256_ps): Ditto. (_mm_avx512_slli_epi32): Ditto. (_mm256_avx512_slli_epi32): Ditto. (_mm_avx512_cvtepi16_epi32): Ditto. (_mm256_avx512_cvtep

[PATCH 2/4] [PATCH 2/3] Change internal intrin call for AVX512 intrins

gcc/ChangeLog: * config/i386/avx512bf16vlintrin.h: Change intrin call. * config/i386/avx512fintrin.h (_mm_avx512_undefined_ps): New. (_mm_avx512_undefined_pd): Ditto. (__attribute__): Change intrin call. * config/i386/avx512vbmivlintrin.h: Ditto.

[PATCH 4/4] Push no-evex512 target for 128/256 bit intrins

gcc/ChangeLog: PR target/111889 * config/i386/avx512bf16intrin.h: Push no-evex512 target. * config/i386/avx512bf16vlintrin.h: Ditto. * config/i386/avx512bitalgvlintrin.h: Ditto. * config/i386/avx512bwintrin.h: Ditto. * config/i386/avx512dqintrin.h: D

[PATCH 0/4] Fix no-evex512 function attribute

Hi all, These four patches are going to fix no-evex512 function attribute. The detail of the issue comes following: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111889 My proposal for this problem is to also push "no-evex512" when defining 128/256 intrins in AVX512. Besides, I added some new in

Re: [PATCH 1/2] match.pd: Support combine cond_len_op + vec_cond similar to cond_op

Committed, thanks Jeff. On 2023/9/28 6:24, Jeff Law wrote: On 9/20/23 07:09, Lehua Ding wrote: This patch adds combine cond_len_op and vec_cond to cond_len_op like cond_op. gcc/ChangeLog: * gimple-match.h (gimple_match_op::gimple_match_op): Add interfaces for more arguments. (gi

Re: [PATCH 2/2] RISC-V: Add assert of the number of vmerge in autovec cond testcases

Committed, thanks Jeff. On 2023/10/17 11:19, Lehua Ding wrote: Hi Jeff, Can you replace riscv_vector with riscv_v?  That way this will still work after Joern commits his change to standardize on the riscv_v target selector. OK with that change, no need to wait for a review on V2, just go ah

Re: Re: [PATCH V5] RISC-V: Implement RESOLVE_OVERLOADED_BUILTIN for RVV intrinsic

Since the following three instances share the class binop, I cannot distinguish between vadd and vfadd. I think it is difficult to add maybe_require_frm_p and maybe_require_vxrm_p to function_base. static CONSTEXPR const binop vadd_obj; static CONSTEXPR const binop vfadd_obj; static CONSTEXPR

Re: [PATCH] RISC-V: Add the missed combine of [u]int64 -> _Float16 and vcond

Committed, thanks Juzhe. On 2023/10/31 11:43, juzhe.zh...@rivai.ai wrote: LGTM. juzhe.zh...@rivai.ai *From:* Lehua Ding *Date:* 2023-10-31 11:39 *To:* gcc-patches

Re: [PATCH] RISC-V: Add the missed combine of [u]int64 -> _Float16 and vcond

LGTM. juzhe.zh...@rivai.ai From: Lehua Ding Date: 2023-10-31 11:39 To: gcc-patches CC: juzhe.zhong; kito.cheng; rdapp.gcc; palmer; jeffreyalaw; lehua.ding Subject: [PATCH] RISC-V: Add the missed combine of [u]int64 -> _Float16 and vcond Hi, This patch let the INT64 to FP16 convert split to

[PATCH] RISC-V: Add the missed combine of [u]int64 -> _Float16 and vcond

Hi, This patch let the INT64 to FP16 convert split to two small converts (INT64 -> FP32 and FP32 -> FP16) when expanding instead of dealy the split to split1 pass. This change could make it possible to combine the FP32 to FP16 and vcond patterns and so we don't need to add an combine pattern for I

Re: Re: [PATCH 2/4] [ifcvt] if convert x=c ? y+z : y by RISC-V Zicond like insns

On 2023-10-31 03:16  Jeff Law wrote: > > > >On 10/30/23 01:25, Fei Gao wrote: >> Conditional add, if zero >> rd = (rc == 0) ? (rs1 + rs2) : rs1 >> --> >> czero.nez rd, rs2, rc >> add rd, rs1, rd >> >> Conditional add, if non-zero >> rd = (rc != 0) ? (rs1 + rs2) : rs1 >> --> >> czero.eqz rd, rs2, r

Re: [committed] d: Merge upstream dmd, druntime e48bc0987d, phobos 2458e8f82.

Excerpts from Rainer Orth's message of Oktober 30, 2023 5:37 pm: > Hi Iain, > >> This patch merges the D front-end and runtime library with upstream dmd >> e48bc0987d, and standard library with phobos 2458e8f82. >> >> Synchronizing with the v2.106.0-beta.1 release. >> >> D front-end changes: >> >>

Re: Re: [PATCH 2/4] [ifcvt] if convert x=c ? y+z : y by RISC-V Zicond like insns

On 2023-10-31 00:36  Jeff Law wrote: > > > >On 10/30/23 01:25, Fei Gao wrote: >> Conditional add, if zero >> rd = (rc == 0) ? (rs1 + rs2) : rs1 >> --> >> czero.nez rd, rs2, rc >> add rd, rs1, rd >> >> Conditional add, if non-zero >> rd = (rc != 0) ? (rs1 + rs2) : rs1 >> --> >> czero.eqz rd, rs2, r

Re: Re: [PATCH v2] RISC-V: Fix ICE of RVV vget/vset intrinsic[PR111935]

Already backported to releases/gcc-13. -- Li Xu >Ok for gcc 13 but just wait one more week to make sure everything is fine >as gcc convention :) > >Li Xu 於 2023年10月24日 週二，15:49寫道： > >> Committed to trunk. Thanks juzhe. >> >> >> -- >> >>

Re: [PATCH] rs6000, Add missing overloaded bcd builtin tests

Hi Carl, on 2023/10/31 08:08, Carl Love wrote: > GCC maintainers: > > The following patch adds tests for two of the rs6000 overloaded built- > ins that do not have tests. Additionally the GCC documentation file I just found that actually they have the test coverage, because we have #define __b

[PATCH V5] RISC-V: Implement RESOLVE_OVERLOADED_BUILTIN for RVV intrinsic

From: xuli Update in v5: * Split has_vxrm_or_frm_p into maybe_require_frm_p and maybe_require_vxrm_p. * Adjust comments. Update in v4: * Remove class function_resolver. * Remove function get_non_overloaded_instance. * Add overloaded hash traits for non-overloaded intrinsic. * All overloaded in

Re: [RFC] RISC-V: Support -mcmodel=large.

> Overall it looks pretty good. Does Andestech have a copyright > assignment in place? Or are you contributing under the DCO rule? Kuan-Lin Chen is Andestech folk, and Andestech have signed copyright assignment for most GNU toolchain components I believe :) > https://gcc.gnu.org/dco.html > > J

Re: Re: [PATCH] RISC-V: Add vector fmin/fmax expanders.

LGTM as long as you add HONOR_SNANS juzhe.zh...@rivai.ai From: Robin Dapp Date: 2023-10-31 03:26 To: Joseph Myers CC: rdapp.gcc; gcc-patches; palmer; Kito Cheng; jeffreyalaw; juzhe.zh...@rivai.ai Subject: Re: [PATCH] RISC-V: Add vector fmin/fmax expanders. > Aren't they actually the IEEE 754

Re: [PATCH 1/4] RISC-V: Recategorize "prefetch" availabilities

> Unless Kito feels otherwise I would suggest keeping a distinct API > interface for each case. Yeah, I think they should have a distinct API.

[PATCH 2/2] RISC-V: Require a extension for testcases with atomic insns

Add testsuite infrastructure for the A extension and use it to require the A extension for dg-do run and add the add extension for non-A dg-do compile. gcc/testsuite/ChangeLog: * gcc.target/riscv/amo-table-a-6-amo-add-1.c: Add A extension to dg-options for dg-do compile. *

[PATCH 1/2] RISC-V: Let non-atomic targets use optimized amo loads/stores

Non-atomic targets are currently prevented from using the optimized fencing for seq_cst load/seq_cst store. This patch removes that constraint. gcc/ChangeLog: * config/riscv/sync-rvwmo.md (atomic_load_rvwmo): Remove TARGET_ATOMIC constraint (atomic_store_rvwmo): Ditto.

[PATCH] RISC-V: Enable ztso tests on rv32

This patch transitions the ztso testcases to use the testsuite infrastructure, enabling the tests on both rv64 and rv32 targets. gcc/testsuite/ChangeLog: * gcc.target/riscv/amo-table-ztso-amo-add-1.c: Add Ztso extension to dg-options for dg-do compile. * gcc.target/riscv/a

[PATCH v2 2/4] Output file checksums in CodeView section

Outputs the file name and MD5 hash of the main source file into the CodeView .debug$S section, along with that of any #include'd files. --- gcc/dwarf2codeview.cc | 254 ++ gcc/dwarf2codeview.h | 1 + gcc/dwarf2out.cc | 5 + 3 files changed, 260 ins

[PATCH v2 1/4] Support for CodeView debugging format

This patch and the following add initial support for Microsoft's CodeView debugging format, as used by MSVC, to mingw targets. Note that you will need a recent version of binutils for this to be useful. The best way to view the output is to run Microsoft's cvdump.exe, found in their microsoft-pdb

[PATCH v4 4/4] Output S_COMPILE3 symbol in CodeView debug section

Outputs the S_COMPILE3 symbol in the CodeView .debug$S debug section. The DEBUG_S_SYMBOLS block added here makes up pretty much everything that isn't data structures or line numbers; we add the S_COMPILE3 symbol here to start it off. This is a descriptive bit, the most interesting part of which is

[PATCH v2 3/4] Output line numbers in CodeView section

Outputs the DEBUG_S_LINES block in the CodeView .debug$S section, which maps between line numbers and addresses. You'll need a fairly recent version of GAS for the .secidx directive to be recognized. --- gcc/dwarf2codeview.cc | 303 ++ gcc/dwarf2codeview.h

[PATCH v2 0/4] CodeView patches

Changes from initial version: * First patch now accepted * Added #ifdefs to avoid compilation failures on other targets

[PATCH] rs6000, Add missing overloaded bcd builtin tests

GCC maintainers: The following patch adds tests for two of the rs6000 overloaded built- ins that do not have tests. Additionally the GCC documentation file doc/extend.texi is updated to include the built-in definitions as they were missing. The patch has been tested on a Power 10 system with no

Re: [PATCH v3] RISC-V: elide unnecessary sign extend when expanding cmp_and_jump

On 10/30/23 13:33, Jeff Law wrote: On 10/29/23 21:21, Vineet Gupta wrote: RV64 compare and branch instructions only support 64-bit operands. At Expand time, the backend conservatively zero/sign extends its operands even if not needed, such as incoming 32-bit function args which ABI/ISA guar

Re: [2/3] [aarch64] Add function multiversioning support

Andrew Carlotti writes: > This adds initial support for function multiversion on aarch64 using the > target_version and target_clones attributes. This mostly follows the > Beta specification in the ACLE [1], with a few diffences that remain to > be fixed: > > - Symbol mangling for target_clones di

Re: [PATCH v2] c: don't emit -Wmissing-variable-declarations for register variables [PR110947]

ping On Fri, Sep 1 2023 at 03:02:41 PM -04:00:00, Hamza Mahfooz wrote: Resolves: PR c/110947 - Should -Wmissing-variable-declarations not trigger on register variables? gcc/c/ChangeLog: PR c/110947 * c-decl.cc (start_decl): don't emit -Wmissing-variable-declarations f

Re: [PATCH 1/4] RISC-V: Recategorize "prefetch" availabilities

On 10/23/23 01:22, Tsukasa OI wrote: From: Tsukasa OI Because they are for all prefetch instructions, "prefetch" fits better than "prefetchi". But there's a significant difference between the cases. prefetch.i in particular fetches into the icache. While prefetch.r and prefetch.w would

Re: [PATCH 0/2] RISC-V: Define not broken prefetch builtins

On 10/22/23 21:55, Tsukasa OI wrote: What I still don't understand is why we're dealing with a decomposed address in the builtin, define_expand and/or define_insn. Sorry, I misunderstood your intent (quite badly) possibly because I was not familiar with the concept of "predicates" in GCC.

Re: [PATCH] [x86_64]: Zhaoxin yongfeng enablement

On Mon, Oct 30, 2023 at 10:08 AM Mayshao-oc wrote: > > >On Fri, Oct 27, 2023 at 12:20 PM mayshao wrote: > >> > >> On 2023/10/26 17:34, Uros Bizjak wrote: > >> > On Wed, Oct 25, 2023 at 8:43 AM mayshao wrote: > >> >> > >> >> Hi all: > >> >> This patch enables -march/-mtune=yongfeng, costs an

Re: [PATCH] genemit: Split insn-emit.cc into ten files.

On 10/27/23 13:04, Robin Dapp wrote: After working with Sam off-list (thanks) I managed to get hppa to build. Initially it looked as if hppa just had a very small number of instruction patterns so we wouldn't generate all 10 output files. However, the actual issue (which we will only hit with

Re: [RFC] RISC-V: Support -mcmodel=large.

On 10/25/23 19:49, KuanLin Chen wrote: This is a RFC patch for large code model implementation. gcc/ChangeLog: * gcc/config/riscv/predicates.md(move_operand): Check SYMBOL_REF and LABEL_REF type. (call_insn_operand): Support for CM_Large. (pcrel_symbol_operand): New. * gcc/config/riscv/riscv-

Re: [RFC PATCH v1] c: Do not warn about external declaration following inline definition

On Mon, 30 Oct 2023, Barnabás Pőcze wrote: > Hi > > > 2023. október 30., hétfő 19:01 keltezéssel, Joseph Myers írta: > > > On Sat, 28 Oct 2023, Barnabás Pőcze wrote: > > > > > An external declaration following an inline definition is not redundant > > > because it forces the compiler to emit a

Re: [PATCH 2/3] MATCH: Move jump_function_from_stmt support to match.pd

On Mon, Oct 30, 2023 at 2:29 AM Richard Biener wrote: > > On Sun, Oct 29, 2023 at 5:41 PM Andrew Pinski wrote: > > > > This moves the value_replacement support for jump_function_from_stmt > > to match pattern. > > This allows us to optimize things earlier in phiopt1 rather than waiting > > to phi

Re: [PATCH v3] RISC-V: elide unnecessary sign extend when expanding cmp_and_jump

On 10/29/23 21:21, Vineet Gupta wrote: RV64 compare and branch instructions only support 64-bit operands. At Expand time, the backend conservatively zero/sign extends its operands even if not needed, such as incoming 32-bit function args which ABI/ISA guarantee to be sign-extended already. An

Re: [PATCH] Testsuite, i386: Fix test by passing -march

> Well It can fail on x86_64-linux-gnu too if GCC was configured with > --with-arch=core2 for an example. > So having it, in this case, not being darwin specific would be > beneficial for all x86_64/i?86 targets. I pushed it as-is, meaning it will indeed apply to all x86_64/i?86 targets. FX

Re: [RFC PATCH v1] c: Do not warn about external declaration following inline definition

Hi 2023. október 30., hétfő 19:01 keltezéssel, Joseph Myers írta: > On Sat, 28 Oct 2023, Barnabás Pőcze wrote: > > > An external declaration following an inline definition is not redundant > > because it forces the compiler to emit an external definition for the > > function. > > That is, > >

[PATCH v5] bpf: Improvements in CO-RE builtins implementation.

Hi everyone, Please find a new version for the review as inline attachment. Best regards, Cupertino Changes from v4: - Implemented TARGET_DELEGITIMIZE_ADDRESS target hook as the proper solution to the the warning for UNSPEC_CORE_RELOC being non-delegitimize. commit 5b45d225c473827b5ef7001e

Re: [PATCH] RISC-V: Add vector fmin/fmax expanders.

> Aren't they actually the IEEE 754-2019 operations (with different > signaling NaN semantics; C functions such as fmaximum in C23), not the > IEEE 754-2008 operations (C functions such as fmax)? V spec 1.0 says "The > vector floating-point vfmin and vfmax instructions have the same behavior >

Re: [PATCH 2/4] [ifcvt] if convert x=c ? y+z : y by RISC-V Zicond like insns

On 10/30/23 01:25, Fei Gao wrote: Conditional add, if zero rd = (rc == 0) ? (rs1 + rs2) : rs1 --> czero.nez rd, rs2, rc add rd, rs1, rd Conditional add, if non-zero rd = (rc != 0) ? (rs1 + rs2) : rs1 --> czero.eqz rd, rs2, rc add rd, rs1, rd Co-authored-by: Xiao Zeng gcc/ChangeLog:

Re: [committed][_GLIBCXX_INLINE_VERSION] Fix constract violation

On Mon, 30 Oct 2023, 18:31 François Dumont, wrote: > > On 30/10/2023 14:45, Jonathan Wakely wrote: > > On Sun, 29 Oct 2023 at 21:11, François Dumont > wrote: > >> This fixes handle_contract_violation under versioned namespace mode. > >> > >> Tested under Linux x64 and confirmed to also fix Darwi

Re: [committed][_GLIBCXX_INLINE_VERSION] Add emul TLS symbol exports

On Mon, 30 Oct 2023, 18:07 François Dumont, wrote: > > On 30/10/2023 14:58, Jonathan Wakely wrote: > > On Sun, 29 Oct 2023 at 21:25, François Dumont > wrote: > >> libstdc++: [_GLIBCXX_INLINE_VERSION] Add emul TLS symbols > >> > >> libstdc++-v3/ChangeLog: > >> > >> * config/abi/pre/gnu-vers

Re: Darwin: Replace environment runpath with embedded [PR88590]

Hi Folks > On 30 Oct 2023, at 16:31, FX Coudert wrote: > >> +enable_darwin_at_rpath_$1=no > > I actually don’t understand why this one would have $1 in the name, unlike > all other regenerated configure files. What value do we expect for $1 at this > point in the file? That’s just plain weird

Re: [PATCH] Testsuite, i386: Fix test by passing -march

On Mon, Oct 30, 2023 at 5:05 AM Iain Sandoe wrote: > > > > > On 30 Oct 2023, at 11:53, FX Coudert wrote: > > > The newly introduced test gcc.target/i386/pr111698.c currently fails on > > Darwin, where the default arch is core2. > > Andrew suggested in https://gcc.gnu.org/bugzilla/show_bug.cgi?id

Re: [PATCH 4/4] [ifcvt] if convert x=c ? y&z : y by RISC-V Zicond like insns

On 10/30/23 01:25, Fei Gao wrote: Conditional and, if zero rd = (rc == 0) ? (rs1 & rs2) : rs1 --> and rd, rs1, rs2 czero.eqz rtmp, rs1, rc or rd, rd, rtmp Conditional and, if non-zero rd = (rc != 0) ? (rs1 & rs2) : rs1 --> and rd, rs1, rs2 czero.nez rtmp, rs1, rc or rd, rd, rtmp Co-authored-

Re: [PATCH 2/4] [ifcvt] if convert x=c ? y+z : y by RISC-V Zicond like insns

On 10/30/23 01:25, Fei Gao wrote: Conditional add, if zero rd = (rc == 0) ? (rs1 + rs2) : rs1 --> czero.nez rd, rs2, rc add rd, rs1, rd Conditional add, if non-zero rd = (rc != 0) ? (rs1 + rs2) : rs1 --> czero.eqz rd, rs2, rc add rd, rs1, rd Co-authored-by: Xiao Zeng gcc/ChangeLog:

Re: [PATCH6/8] omp: Reorder call for TARGET_SIMD_CLONE_ADJUST (was Re: [PATCH7/8] vect: Add TARGET_SIMD_CLONE_ADJUST_RET_OR_PARAM)

Hi Richi, Friendly ping on this. I'm going away for two weeks end of this week, so I won't be here for end of stage-1, but I'd still very much like to get this done for GCC 14. I don't know if you had a chance to look at this yet when you reviewed the other patches or if you maybe just misse

Re: [committed][_GLIBCXX_INLINE_VERSION] Fix constract violation

On 30/10/2023 14:45, Jonathan Wakely wrote: On Sun, 29 Oct 2023 at 21:11, François Dumont wrote: This fixes handle_contract_violation under versioned namespace mode. Tested under Linux x64 and confirmed to also fix Darwin build. libstdc++: [_GLIBCXX_INLINE_VERSION] Provide handle_contract_v

Re: [PATCH] RISC-V: Add vector fmin/fmax expanders.

On Mon, 30 Oct 2023, Robin Dapp wrote: > Hi, > > this patch adds expanders for fmin and fmax and the associated > cond and reduc ones. As per RISC-V V spec 1.0 vfmin/vfmax are > IEEE 754-2008 compliant so that should be ok. Aren't they actually the IEEE 754-2019 operations (with different sign

Re: [committed][_GLIBCXX_INLINE_VERSION] Add emul TLS symbol exports

On 30/10/2023 14:58, Jonathan Wakely wrote: On Sun, 29 Oct 2023 at 21:25, François Dumont wrote: libstdc++: [_GLIBCXX_INLINE_VERSION] Add emul TLS symbols libstdc++-v3/ChangeLog: * config/abi/pre/gnu-versioned-namespace.ver: Add missing emul TLS symbols. Please put a comment a

Re: [RFC PATCH v1] c: Do not warn about external declaration following inline definition

On Sat, 28 Oct 2023, Barnabás Pőcze wrote: > An external declaration following an inline definition is not redundant > because it forces the compiler to emit an external definition for the > function. > That is, > > inline void f(void) { } > [extern] void f(void); > > should not trigger the

Re: [PATCH 2/3] ipa: Prune any IPA-CP aggregate constants known by modref to be killed (111157)

Hello, On Thu, Oct 05 2023, Jan Hubicka wrote: >> gcc/ChangeLog: >> >> 2023-09-19 Martin Jambor >> >> PR ipa/57 >> * ipa-prop.h (struct ipa_argagg_value): Newf flag killed. >> * ipa-modref.cc (ipcp_argagg_and_kill_overlap_p): New function. >> (update_signature): Mark a

[x86_64 PATCH] PR target/110551: Tweak mulx register allocation using peephole2.

This patch is a follow-up to my previous PR target/110551 patch, this time to address the additional move after mulx, seen on TARGET_BMI2 architectures (such as -march=haswell). The complication here is that the flexible multiple-set mulx instruction is introduced into RTL after reload, by split2

[PATCH v6 1/1] gcc: config: microblaze: fix cpu version check

The MICROBLAZE_VERSION_COMPARE was incorrectly using strcasecmp instead of strverscmp to check the mcpu version against feature options. By simply changing the define to use strverscmp, the new version 10.0 is treated correctly as a higher version than previous versions. Signed-off-by: Neal Frage

[Committed] RISC-V: Make rv32i_zcmp testcase more robust

On 10/30/23 09:55, Jeff Law wrote: On 10/30/23 10:37, Patrick O'Neill wrote: GCC recently changed its register allocator which causes this testcase to fail. This patch updates the regex to be more robust to change by accepting any s register in the range of 1-9 for cm.push and cm.popret insn

Re: [PATCH] RISC-V: Make rv32i_zcmp testcase more robust

On 10/30/23 10:37, Patrick O'Neill wrote: GCC recently changed its register allocator which causes this testcase to fail. This patch updates the regex to be more robust to change by accepting any s register in the range of 1-9 for cm.push and cm.popret insns. gcc/testsuite/ChangeLog:

Re: [PATCH v3] RISC-V: elide unnecessary sign extend when expanding cmp_and_jump

On 10/29/23 20:21, Vineet Gupta wrote: RV64 compare and branch instructions only support 64-bit operands. At Expand time, the backend conservatively zero/sign extends its operands even if not needed, such as incoming 32-bit function args which ABI/ISA guarantee to be sign-extended already. And

Re: [committed] d: Merge upstream dmd, druntime e48bc0987d, phobos 2458e8f82.

Hi Iain, > This patch merges the D front-end and runtime library with upstream dmd > e48bc0987d, and standard library with phobos 2458e8f82. > > Synchronizing with the v2.106.0-beta.1 release. > > D front-end changes: > > - Import dmd v2.106.0-beta.1. this patch broke D bootstrap, it seems:

[PATCH] RISC-V: Make rv32i_zcmp testcase more robust

GCC recently changed its register allocator which causes this testcase to fail. This patch updates the regex to be more robust to change by accepting any s register in the range of 1-9 for cm.push and cm.popret insns. gcc/testsuite/ChangeLog: * gcc.target/riscv/rv32i_zcmp.c: Accept any re

Re: [PATCH 2/4] [ifcvt] if convert x=c ? y+z : y by RISC-V Zicond like insns

On 10/30/23 01:25, Fei Gao wrote: Conditional add, if zero rd = (rc == 0) ? (rs1 + rs2) : rs1 --> czero.nez rd, rs2, rc add rd, rs1, rd Conditional add, if non-zero rd = (rc != 0) ? (rs1 + rs2) : rs1 --> czero.eqz rd, rs2, rc add rd, rs1, rd Co-authored-by: Xiao Zeng gcc/ChangeLog:

Re: Darwin: Replace environment runpath with embedded [PR88590]

Hi, > +enable_darwin_at_rpath_$1=no I actually don’t understand why this one would have $1 in the name, unlike all other regenerated configure files. What value do we expect for $1 at this point in the file? That’s just plain weird. FX

[PATCH v6 1/1] gcc: config: microblaze: fix cpu version check

The MICROBLAZE_VERSION_COMPARE was incorrectly using strcasecmp instead of strverscmp to check the mcpu version against feature options. By simply changing the define to use strverscmp, the new version 10.0 is treated correctly as a higher version than previous versions. Signed-off-by: Neal Frage

Re: Darwin: Replace environment runpath with embedded [PR88590]

Hi Martin, > On 30 Oct 2023, at 16:17, Martin Jambor wrote: > On Tue, Aug 15 2023, FX Coudert via Gcc-patches wrote: >> > > [...] > >> From e1cf04cadb9fa065fb3f7d6bccf9ed6f1e9e3fc1 Mon Sep 17 00:00:00 2001 >> From: Iain Sandoe >> Date: Sun, 28 Mar 2021 14:48:17 +0100 >> Subject: [PATCH 2/4]

Re: Darwin: Replace environment runpath with embedded [PR88590]

Hello Iain, On Tue, Aug 15 2023, FX Coudert via Gcc-patches wrote: > [...] > From e1cf04cadb9fa065fb3f7d6bccf9ed6f1e9e3fc1 Mon Sep 17 00:00:00 2001 > From: Iain Sandoe > Date: Sun, 28 Mar 2021 14:48:17 +0100 > Subject: [PATCH 2/4] Darwin: Allow for configuring Darwin to use embedded > runpath.

Re: [PATCH v5 1/1] gcc: config: microblaze: fix cpu version check

On 10/29/23 23:13, Neal Frager wrote: The MICROBLAZE_VERSION_COMPARE was incorrectly using strcasecmp instead of strverscmp to check the mcpu version against feature options. By simply changing the define to use strverscmp, the new version 10.0 is treated correctly as a higher version than previ

[PATCH] RISC-V: Add vector fmin/fmax expanders.

Hi, this patch adds expanders for fmin and fmax and the associated cond and reduc ones. As per RISC-V V spec 1.0 vfmin/vfmax are IEEE 754-2008 compliant so that should be ok. Regards Robin gcc/ChangeLog: * config/riscv/autovec.md (3): fmax/fmin expanders. (cond_): Ditt

Re: [ARC PATCH] Improve DImode left shift by a single bit.

On 10/30/23 09:27, Roger Sayle wrote: WRT H8. Bug filed so we don't lose track of it. We don't have DImode operations defined on the H8. First step would be DImode loads/stores and basic arithmetic. The H8's machine description is impressively well organized. Would it make sense to add

RE: [ARC PATCH] Improve DImode left shift by a single bit.

Hi Jeff, > From: Jeff Law > Sent: 30 October 2023 15:09 > Subject: Re: [ARC PATCH] Improve DImode left shift by a single bit. > > On 10/28/23 07:05, Roger Sayle wrote: > > > > This patch improves the code generated for X << 1 (and for X + X) when > > X is 64-bit DImode, using the same two instruc

Re: [PATCH 1/4] [RISC-V]add hook to control Zicond based ifcvt opt

On 10/30/23 01:25, Fei Gao wrote: TARGET_HAVE_COND_ZERO is added to control ifcvt optimization for targets with RISC-V Zicond like insns. Co-authored-by: Xiao Zeng gcc/ChangeLog: * config/riscv/riscv.cc (riscv_have_cond_zero): Implement TARGET_HAVE_COND_ZERO (TARGET_HAVE_

[committed][wwwdocs] Uncomment link to "Porting to GCC 14"

Pushed to wwwdocs. -- >8 -- --- htdocs/gcc-14/changes.html | 2 -- 1 file changed, 2 deletions(-) diff --git a/htdocs/gcc-14/changes.html b/htdocs/gcc-14/changes.html index 5611fc4f..e5d3970c 100644 --- a/htdocs/gcc-14/changes.html +++ b/htdocs/gcc-14/changes.html @@ -17,11 +17,9 @@ This pag

[committed][wwwdocs] Add "Porting to GCC 14"

Pushed to wwwdocs. -- >8 -- --- htdocs/gcc-14/porting_to.html | 50 +++ 1 file changed, 50 insertions(+) create mode 100644 htdocs/gcc-14/porting_to.html diff --git a/htdocs/gcc-14/porting_to.html b/htdocs/gcc-14/porting_to.html new file mode 100644 index 00

Re: [ARC PATCH] Improve DImode left shift by a single bit.

On 10/28/23 07:05, Roger Sayle wrote: This patch improves the code generated for X << 1 (and for X + X) when X is 64-bit DImode, using the same two instruction code sequence used for DImode addition. For the test case: long long foo(long long x) { return x << 1; } GCC -O2 currently generat

[PATCH V2] aarch64: Implement the ACLE instruction/data prefetch functions.

Correct CV-qualification from being erroeously applied to the `addr' pointer, applying it instead to its pointer target, as specified by the ACLE standards. --- Implement the ACLE data and instruction prefetch functions[1] with the following signatures: 1. Data prefetch intrinsics: -

Re: [ARC PATCH] Improved ARC rtx_costs/insn_cost for SHIFTs and ROTATEs.

On 10/29/23 03:16, Roger Sayle wrote: This patch overhauls the ARC backend's insn_cost target hook, and makes some related improvements to rtx_costs, BRANCH_COST, etc. The primary goal is to allow the backend to indicate that shifts and rotates are slow (discouraged) when the CPU doesn't hav

Re: [PATCH] Testsuite, i386: Mark test as requiring ifunc

On Mon, Oct 30, 2023 at 3:43 PM FX Coudert wrote: > > Hi, > > The test is currently failing on x86_64-apple-darwin. > Marking the test as requiring ifunc fixes the issue. > > OK to push? OK. > > FX >

[PATCH] Testsuite, i386: Mark test as requiring ifunc

Hi, The test is currently failing on x86_64-apple-darwin. Marking the test as requiring ifunc fixes the issue. OK to push? FX 0001-Testsuite-i386-Mark-test-as-requiring-ifunc.patch Description: Binary data

[PATCH] Testsuite, i386: Mark test as requiring dfp

Hi, The test is currently failing on x86_64-apple-darwin with "decimal floating-point not supported for this target”. Marking the test as requiring dfp fixes the issue. OK to push? FX 0001-Testsuite-i386-Mark-test-as-requiring-dfp.patch Description: Binary data

Re: [committed][_GLIBCXX_INLINE_VERSION] Add emul TLS symbol exports

On Sun, 29 Oct 2023 at 21:25, François Dumont wrote: > > libstdc++: [_GLIBCXX_INLINE_VERSION] Add emul TLS symbols > > libstdc++-v3/ChangeLog: > > * config/abi/pre/gnu-versioned-namespace.ver: Add missing emul TLS > symbols. Please put a comment above the two new lines, the same as in

Re: [PATCH] Testsuite, Darwin: Fix trampoline warning

Hi FX, > On 30 Oct 2023, at 13:50, FX Coudert wrote: > > Heap-based trampolines are enabled on darwin20 and later, meaning that no > warning is emitted. > Fixes the test failure on x86_64-apple-darwin21 > > OK to push? OK, thanks Iain

Re: [ARC PATCH] Convert (signed<<31)>>31 to -(signed&1) without barrel shifter.

Hi Roger, Do you want to say bmsk_s instead of msk_s here: +/* { dg-final { scan-assembler "msk_s\\s+r0,r0,0" } } */ Anyhow, the patch looks good. Proceed with your commit. Thank you, Claudiu On Mon, Oct 30, 2023 at 5:05 AM Jeff Law wrote: > > > > On 10/28/23 10:47, Roger Sayle wrote: > > > >

[PATCH] Testsuite, Darwin: Fix trampoline warning

Heap-based trampolines are enabled on darwin20 and later, meaning that no warning is emitted. Fixes the test failure on x86_64-apple-darwin21 OK to push? FX 0001-Testsuite-Darwin-Fix-trampoline-warning.patch Description: Binary data

Re: [ARC PATCH] Improved ARC rtx_costs/insn_cost for SHIFTs and ROTATEs.

Hi Roger, You have a block of 8 spaces that needs to be replaced by tabs: gcc/config/arc/arc.cc:5538:0: if (n < 4) Please fix the above, and proceed with your commit. Thank you, Claudiu On Sun, Oct 29, 2023 at 11:16 AM Roger Sayle wrote: > > > This patch overhauls the ARC backend's insn_

Re: [committed][_GLIBCXX_INLINE_VERSION] Fix constract violation

On Sun, 29 Oct 2023 at 21:11, François Dumont wrote: > > This fixes handle_contract_violation under versioned namespace mode. > > Tested under Linux x64 and confirmed to also fix Darwin build. > > libstdc++: [_GLIBCXX_INLINE_VERSION] Provide handle_contract_violation > symbol > > libstdc++-v3/Chan

[PING][PATCH RFA] PR target/111815: VAX: Only accept the index scaler as the RHS operand to ASHIFT

On Mon, 16 Oct 2023, Maciej W. Rozycki wrote: > The testcase is generic enough I thought it wouldn't hurt to place it in > a generic part of the testsuite, where it has been verified to pass with > the `powerpc64le-linux-gnu', `riscv64-linux-gnu', and `vax-netbsdelf' > targets. I'm fine to mo

Re: [ARC PATCH] Improved SImode shifts and rotates with -mswap.

Hi Roger, +(define_insn "si2_cnt16" + [(set (match_operand:SI 0 "dest_reg_operand" "=w") Please use "register_operand", and "r" constraint. +(ANY_ROTATE:SI (match_operand:SI 1 "register_operand" "c") Please use "r" constraint instead of "c". + (const_int 16)))] + "TARGET_SW

Re: [PATCH v8] tree-ssa-sink: Improve code sinking pass

On 30/10/23 5:51 pm, Ajit Agarwal wrote: > Hello Richard: > > On 17/10/23 2:47 pm, Richard Biener wrote: >> On Tue, Oct 17, 2023 at 10:53 AM Ajit Agarwal wrote: >>> >>> Hello Richard: >>> >>> On 17/10/23 2:03 pm, Richard Biener wrote: On Thu, Oct 12, 2023 at 10:42 AM Ajit Agarwal w

[PATCH] Assert we don't create recursive DW_AT_abstract_origin

We have a support case that shows GCC 7 sometimes creates DW_TAG_label refering to itself via a DW_AT_abstract_origin when using LTO. This for example triggers the sanity check added below during LTO bootstrap. Making this check cover more than just DW_AT_abstract_origin breaks bootstrap on trunk

Re: [wwwdocs] Get newlib via git in simtest-howto.html

On Fri, Oct 27, 2023 at 6:39 PM Roger Sayle wrote: > > > A minor tweak to the documentation, to use git rather than cvs to obtain > the latest version of newlib. Ok for mainline? OK > > 2023-10-27 Roger Sayle > > * htdocs/simtest-howto.html: Use git to obtain newlib. > > Cheers, > Ro

Re: [PATCH, OpenACC 2.7] Connect readonly modifier to points-to analysis

On Fri, Oct 27, 2023 at 4:28 PM Thomas Schwinge wrote: > > Hi! > > Richard, as the original author of 'SSA_NAME_POINTS_TO_READONLY_MEMORY': > 2018 commit 6214d5c7e7470bdd5ecbeae668c2522551bfebbc (Subversion r263958) > "Move const_parm trick to generic code"; 'gcc/tree.h': > > /* Nonzero if thi

Re: [PATCH] LoongArch: Define HAVE_AS_TLS to 0 if it's undefined

在 2023/10/30 下午8:26, Xi Ruoyao 写道: On Mon, 2023-10-30 at 19:50 +0800, chenglulu wrote: 在 2023/10/30 下午7:42, Xi Ruoyao 写道: Now loongarch.md uses HAVE_AS_TLS, we need this to fix the failure building a cross compiler if the cross assembler is not installed yet. gcc/ChangeLog:   * config

Re: [PATCH] LoongArch: Define HAVE_AS_TLS to 0 if it's undefined

On Mon, 2023-10-30 at 19:50 +0800, chenglulu wrote: > 在 2023/10/30 下午7:42, Xi Ruoyao 写道: > > Now loongarch.md uses HAVE_AS_TLS, we need this to fix the failure > > building a cross compiler if the cross assembler is not installed yet. > > > > gcc/ChangeLog: > > > >   * config/loongarch/loongarc

Re: [PATCH v8] tree-ssa-sink: Improve code sinking pass

Hello Richard: On 17/10/23 2:47 pm, Richard Biener wrote: > On Tue, Oct 17, 2023 at 10:53 AM Ajit Agarwal wrote: >> >> Hello Richard: >> >> On 17/10/23 2:03 pm, Richard Biener wrote: >>> On Thu, Oct 12, 2023 at 10:42 AM Ajit Agarwal >>> wrote: This patch improves code sinking pass to

[PATCH v3] VECT: Refine the type size restriction of call vectorizer

From: Pan Li Update in v3: * Add func to predicate type size is legal or not for vectorizer call. Update in v2: * Fix one ICE of type assertion. * Adjust some test cases for aarch64 sve and riscv vector. Original log: The vectoriable_call has one restriction of the size of data type. Aka DF

[PATCH V11] : tree-ssa-sink: Improve code sinking pass

Hello Richard: Currently, code sinking will sink code at the use points with loop having same nesting depth. The following patch improves code sinking by placing the sunk code in immediate dominator with same loop nest depth. Review comments are incorporated. For example : void bar(); int j; vo

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