From: Pan Li
This patch would like to support auto-vectorization for the
floor API in math.h. It depends on the -ffast-math option.
When we would like to call floor/floorf like v2 = floor (v1), we will
convert it into below insns (reference the implementation of llvm).
* vfcvt.x.f v3, v1, RDN
*
Committed, thanks Juzhe.
Pan
From: juzhe.zhong
Sent: Friday, September 22, 2023 12:18 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; Li, Pan2 ; Wang, Yanzhang
; kito.ch...@gmail.com
Subject: Re: [PATCH v1] RISC-V: Rename the test macro for math autovec test
ok
Replied Message
From
pan
Committed, thanks Juzhe.
--
Li Xu
>LGTM. You can commit it after you pass the regression.
>
>
>
>juzhe.zh...@rivai.ai
>
>From: Li Xu
>Date: 2023-09-22 10:37
>To: gcc-patches
>CC: kito.cheng; palmer; juzhe.zhong; xuli
>Subject: [PATCH V2] RISC-V: Optimization of vrgather.vv into
>vrgath
ok Replied Message Frompan2...@intel.comDate09/22/2023 11:47 Togcc-patches@gcc.gnu.org Ccjuzhe.zh...@rivai.ai,pan2...@intel.com,yanzhang.w...@intel.com,kito.ch...@gmail.comSubject[PATCH v1] RISC-V: Rename the test macro for math autovec test
Committed, thanks Juzhe.
Pan
From: juzhe.zh...@rivai.ai
Sent: Friday, September 22, 2023 11:45 AM
To: Li, Pan2 ; gcc-patches
Cc: Li, Pan2 ; Wang, Yanzhang ;
kito.cheng
Subject: Re: [PATCH v1] RISC-V: Remove arch and abi option for run test case.
LGTM
juzhe.z
From: Pan Li
Rename TEST_CEIL to TEST_UNARY_CALL for the underlying function
autovec patch testing.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/test-math.h: Rename.
* gcc.target/riscv/rvv/autovec/math-ceil-0.c: Ditto.
* gcc.target/riscv/rvv/autovec/math-ceil-
LGTM
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-09-22 11:39
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Remove arch and abi option for run test case.
From: Pan Li
Remove the -march and -mabi.
gcc/testsuite/ChangeLog:
* gcc.target/ri
From: Pan Li
Remove the -march and -mabi.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/math-ceil-run-0.c: Remove arch and abi.
* gcc.target/riscv/rvv/autovec/math-ceil-run-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/math-ceil-run-2.c: Ditto.
Signed-off-by: Pan
On Thu, Sep 21, 2023 at 3:22 PM Hu, Lin1 wrote:
>
> Hi all,
>
> After previous discussion, instead of supporting option -mavx10.1, we
> will first introduct option -m[no-]evex512, which will enable/disable
> 512 bit register and 64 bit mask register.
>
> It will not change the current option behav
Committed with splited patchs, thanks Robin.
[COMMITTED] RISC-V: Split VLS avl_type from NONVLMAX avl_type
https://gcc.gnu.org/pipermail/gcc-patches/2023-September/631152.html
[COMMITTED V4] RISC-V: Support combine cond extend and reduce sum to
widen reduce sum
https://gcc.gnu.org/pipermail/gc
This patch support combining cond extend and reduce_sum to cond widen reduce_sum
like combine the following three insns:
(set (reg:RVVM2HI 149)
(if_then_else:RVVM2HI
(unspec:RVVMF8BI [
(const_vector:RVVMF8BI repeat [
(const_int 1 [0x1])
])
This patch split a VLS avl_type from the NONVLMAX avl_type, denoting
those RVV insn with length set to the number of units of VLS modes.
gcc/ChangeLog:
* config/riscv/riscv-protos.h (enum avl_type): New VLS avl_type.
* config/riscv/riscv-v.cc (autovec_use_vlmax_p): Move comments.
LGTM. You can commit it after you pass the regression.
juzhe.zh...@rivai.ai
From: Li Xu
Date: 2023-09-22 10:37
To: gcc-patches
CC: kito.cheng; palmer; juzhe.zhong; xuli
Subject: [PATCH V2] RISC-V: Optimization of vrgather.vv into
vrgatherei16.vv[PR111451]
From: xuli
Consider this following
From: xuli
Consider this following case:
typedef int32_t vnx32si __attribute__ ((vector_size (128)));
__attribute__ ((noipa)) void permute_##TYPE (TYPE values1, TYPE values2, \
TYPE *out) \
{
Sorry. It should be:
else if (CONST_VECTOR_P (sel)
&& GET_MODE_BITSIZE (GET_MODE_INNER (sel_mode)).to_constant () > 16
&& riscv_get_v_regno_alignment (data_mode) > 1)
juzhe.zh...@rivai.ai
From: juzhe.zh...@rivai.ai
Date: 2023-09-22 09:39
To: Li Xu; gcc-patches
CC: kito.cheng; palmer; Li Xu
S
+ unsigned int data_sew = get_sew (data_mode);
+ enum vlmul_type data_lmul = get_vlmul (data_mode);
Remove this.
+ else if (CONST_VECTOR_P (sel) && data_sew != 16
+ && data_sew != 8 && (data_lmul == LMUL_2
+ || data_lmul == LMUL_4 || data_lmul == LMUL_8))
change it into:
From: xuli
Consider this following case:
typedef int32_t vnx32si __attribute__ ((vector_size (128)));
__attribute__ ((noipa)) void permute_##TYPE (TYPE values1, TYPE values2, \
TYPE *out) \
{
Committed, thanks Juzhe.
Pan
From: juzhe.zh...@rivai.ai
Sent: Friday, September 22, 2023 9:17 AM
To: Li, Pan2 ; gcc-patches
Cc: Li, Pan2 ; Wang, Yanzhang ;
kito.cheng
Subject: Re: [PATCH v1] RISC-V: Leverage __builtin_xx instead of math.h for test
LGTM。
juzh
LGTM。
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-09-22 09:12
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Leverage __builtin_xx instead of math.h for test
From: Pan Li
The math.h may have problems in some environment, take __builtin__xx
From: Pan Li
The math.h may have problems in some environment, take __builtin__xx
instead for testing.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vls/floating-point-max-5.c:
Remove reference to math.h.
* gcc.target/riscv/rvv/autovec/vls/floating-point-min-5.
LGTM
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-09-22 08:12
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v4] RISC-V: Support ceil and ceilf auto-vectorization
From: Pan Li
Update in v4:
* Add test for _Float16.
* Remove unnecessary macro in def.h
From: Pan Li
Update in v4:
* Add test for _Float16.
* Remove unnecessary macro in def.h for test.
Original log:
This patch would like to support auto-vectorization for both the
ceil and ceilf of math.h. It depends on the -ffast-math option.
When we would like to call ceil/ceilf like v2 = ceil
On 18 September 2023 12:19:17 CEST, Julian Brown
wrote:
>On Thu, 14 Sep 2023 17:13:02 +0200
>Bernhard Reutner-Fischer via Gcc-patches
>wrote:
>
>> On Tue, 5 Sep 2023 12:28:28 -0700
>> Julian Brown wrote:
>>
>> > + static bool
>> > + equal (const omp_name_type &a,
>> > + const omp_name_type
Regression passed.
Committed.
gcc/ChangeLog:
* config/riscv/autovec.md: Extend VLS modes.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vls/abs-2.c: New test.
---
gcc/config/riscv/autovec.md | 6 +-
.../gcc.target/riscv/rvv/autovec/vls/abs-2.c |
Add FP16 tests:
https://godbolt.org/z/e9vrzKTvn
Like LLVM.
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
index 74685f8d05e..ccc1d1d70ab 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
+++ b/gcc/testsuit
On 9/21/23 09:14, Patrick O'Neill wrote:
On 9/21/23 03:20, Palmer Dabbelt wrote:
On Wed, 20 Sep 2023 10:47:23 PDT (-0700), Patrick O'Neill wrote:
...
[1]:
Executing on host:
/github/ewlu-runner-2/_work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/build-gcc-linux-stage2/gcc/xgcc
-B/github/e
Hi Juzhe,
I've added this to my TODO once pre-commit patchworks CI is sorted out :)
How often do we want to run these tests?
I was thinking of starting up a once-weekly run of compute-intensive
tasks like --enable-checking=rtl builds/testsuite runs.
If we aren't expecting frequent breakages, i
> From: Qing Zhao
> Date: Tue, 19 Sep 2023 14:19:09 +
> > On Sep 17, 2023, at 12:36 PM, Hans-Peter Nilsson via Gcc-patches
> > wrote:
> >> From: Sam James
> >> Date: Sun, 17 Sep 2023 05:00:37 +0100
> >> Did some bug ever get filed for this to see if we can do a bit
> >> better here?
> >
>
Add support for inline memmove expansions. The generated code is identical
as for memcpy, except that all loads are emitted before stores rather than
being interleaved. The maximum size is 256 bytes which requires at most 16
registers.
Passes regress/bootstrap, OK for commit?
gcc/ChangeLog
On 9/21/23 03:20, Palmer Dabbelt wrote:
On Wed, 20 Sep 2023 10:47:23 PDT (-0700), Patrick O'Neill wrote:
...
[1]:
Executing on host:
/github/ewlu-runner-2/_work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/build-gcc-linux-stage2/gcc/xgcc
-B/github/ewlu-runner-2/_work/riscv-gnu-toolchain/ri
On 9/20/23 10:13, Patrick Palka wrote:
On Tue, 19 Sep 2023, Patrick Palka wrote:
On Tue, 19 Sep 2023, Jason Merrill wrote:
On 9/19/23 12:40, Patrick Palka wrote:
Tested on x86_64-pc-linux-gnu, does this look OK for trunk/13?
OK for trunk. What's your argument for backporting?
Thanks. I
From: Pan Li
This patch would like to support auto-vectorization for both the
ceil and ceilf of math.h. It depends on the -ffast-math option.
When we would like to call ceil/ceilf like v2 = ceil (v1), we will
convert it into below insn (reference the implementation of llvm).
* vfcvt.x.f v3, v1,
v2: Use UINTVAL, rename max_mops_size.
The cpymemdi/setmemdi implementation doesn't fully support strict alignment.
Block the expansion if the alignment is less than 16 with STRICT_ALIGNMENT.
Clean up the condition when to use MOPS.
Passes regress/bootstrap, OK for commit?
gcc/ChangeLog/
I've updated the error messages, and also fixed another bug I found
while retesting (value-initialised unions weren't considered to have any
active member yet).
Bootstrapped and regtested on x86_64-pc-linux-gnu.
-- >8 --
This patch adds checks for attempting to change the active member of a
unio
Notice we are missing these tests.
Committed.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vls/abs-1.c: New test.
* gcc.target/riscv/rvv/autovec/vls/not-1.c: New test.
* gcc.target/riscv/rvv/autovec/vls/sqrt-1.c: New test.
---
.../gcc.target/riscv/rvv/autovec
Regression passed.
Committed.
gcc/ChangeLog:
* config/riscv/vector-iterators.md: Extend VLS modes.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vls/def.h: Add VLS mult high.
* gcc.target/riscv/rvv/autovec/vls/mulh-1.c: New test.
---
gcc/config/riscv/vector-
Hi, Patrick.
GNU rvv intrinsic api test-generator has been merged:
https://github.com/riscv-non-isa/rvv-intrinsic-doc/commits/main
Could you include the full RVV intrinsic API test in your test CI?
Currently, we don't include all API test in the GCC testsuite since it's too
big.
juzhe.zh...@
Also。 Remove math.h include。
Instead, plz use __builtin_ceil.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-09-21 18:32
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v2] RISC-V: Support ceil and ceilf auto-vectorization
From: Pan Li
This patch would lik
> This seems like a reasonable place for it since 'this' is supposed to
> precede the decl-specifiers, and since we are parsing initial attributes
> here rather than in the caller. You will want to give an error if
> found_decl_spec is set. And elsewhere complain about 'this' on
> parameters after
On Thu, 21 Sep 2023 04:24:48 PDT (-0700), kito.ch...@sifive.com wrote:
GCC has built in function[1] for those math function stuff, e.g.
__builtin_ceilf, so we don't really need math.h :)
[1] https://gcc.gnu.org/onlinedocs/gcc/Other-Builtins.html
That's probably the right way to go for the test
GCC has built in function[1] for those math function stuff, e.g.
__builtin_ceilf, so we don't really need math.h :)
[1] https://gcc.gnu.org/onlinedocs/gcc/Other-Builtins.html
On Thu, Sep 21, 2023 at 11:20 AM Palmer Dabbelt wrote:
>
> On Wed, 20 Sep 2023 10:47:23 PDT (-0700), Patrick O'Neill wrot
+(define_expand "ceil2"
+ [(match_operand:V_VLSF 0 "register_operand")
+ (match_operand:V_VLSF 1 "register_operand")]
+ "TARGET_VECTOR"
+ {
+riscv_vector::expand_vec_ceil (operands[0], operands[1], mode,
mode);
+DONE;
+ }
I think you should add !flag_trapping_math && !flag_rounding_
From: Pan Li
This patch would like to support auto-vectorization for both the
ceil and ceilf of math.h. It depends on the -ffast-math option.
When we would like to call ceil/ceilf like v2 = ceil (v1), we will
convert it into below insn (reference the implementation of llvm).
* vfcvt.x.f v3, v1,
On Wed, 20 Sep 2023 10:47:23 PDT (-0700), Patrick O'Neill wrote:
Juzhe,
On a more general note, are we expecting #include to cause a
testcase to fail?
My motivation is to make the testsuite less noisy when checking for
regressions. For example, a patch like this one:
https://patchwork.sourcewa
Committed, thanks Robin.
On 2023/9/21 17:57, Robin Dapp wrote:
LGTM.
Regards
Robin
--
Best,
Lehua (RiVAI)
lehua.d...@rivai.ai
LGTM.
Regards
Robin
Hi Robin,
I once had different comments for those but either I never pushed them
or they got buried in the process of refactoring. The explanatory
comment explaining vlmax is also in "nowhere land" below autovec_use_vlmax_p.
(it says vsetvli instead of vsetvl as well...) It would be useful
to
V2 Change: Use Robin's comments.
This patch adjusts the comments of the
emit_vlmax_insn/emit_vlmax_insn_lra/emit_nonvlmax_insn functions.
The purpose of the adjustment is to make it clear that vlmax here is not
VLMAX as defined inside the RVV ISA. This is because this function is used
by RVV mode
Committed, thanks Robin and Kito.
On 2023/9/21 17:19, Kito Cheng wrote:
Cool, LGTM as well!
On Thu, Sep 21, 2023 at 10:11 AM Robin Dapp wrote:
Hi Juzhe,
with the middle-end changes that's a nice improvement. LGTM.
Regards
Robin
--
Best,
Lehua (RiVAI)
lehua.d...@rivai.ai
Hi Andrew, hi Thomas, hi all,
@Thomas: I wouldn't mind if you could glance at the nvptx/CUDA bits.
On 12.09.23 16:27, Andrew Stubbs wrote:
This patch implements parallel execution of OpenMP reverse offload
kernels.
...
The device threads that sent requests are still blocked waiting for
the comp
This updates for newer features implemented very recently (project status)
and since a while (gcc-14/changes/).
Comments? Remarks? Suggestions?
I not, I plan to commit it relatively soon - but follow-up changes are
of course possible :-)
Tobias
-
Siemens Electronic Design Automa
Cool, LGTM as well!
On Thu, Sep 21, 2023 at 10:11 AM Robin Dapp wrote:
>
> Hi Juzhe,
>
> with the middle-end changes that's a nice improvement. LGTM.
>
> Regards
> Robin
Pushed the patches to trunk.
Thank you both for the review.
Kindly,
Arthur
On 9/14/23 12:12, Richard Biener via Gcc-rust wrote:
On Wed, Sep 13, 2023 at 10:14 PM Iain Buclaw via Gcc-patches
wrote:
Excerpts from Arthur Cohen's message of September 7, 2023 3:41 pm:
Alright, was not expecting
Hi Juzhe,
with the middle-end changes that's a nice improvement. LGTM.
Regards
Robin
Hi Lehua,
I once had different comments for those but either I never pushed them
or they got buried in the process of refactoring. The explanatory
comment explaining vlmax is also in "nowhere land" below autovec_use_vlmax_p.
(it says vsetvli instead of vsetvl as well...) It would be useful
to mo
On Thu, Sep 21, 2023 at 10:44:30AM +0200, Arthur Cohen wrote:
> From: Pierre-Emmanuel Patry
>
> Resending this patch without most of the diff so it fits on the ML.
>
> -
>
> Regenerate all build files.
>
> ChangeLog:
>
> * Makefile.in:
Missing Regenerate. above?
> * configur
From: Pierre-Emmanuel Patry
Resending this patch without most of the diff so it fits on the ML.
-
Regenerate all build files.
ChangeLog:
* Makefile.in:
* configure: Regenerate.
* libgrust/Makefile.in: New file.
* libgrust/aclocal.m4: New file.
* lib
Hi Robin,
On 2023/9/21 16:12, Robin Dapp wrote:
Hi Lehua,
V3 Change: Back to the original method.
Was there an original method even before the first patch?
Yes, this was the method that came to mind at first, and I didn't send a
patch because I didn't feel like the pattern looked good :)
Now GCC middle-end can support undefined value which is traslated into
(scratch:mode).
This patch is to enable RISC-V backend undefine value in ELSE value of
COND_LEN_xxx/COND_xxx.
Consider this following case:
__attribute__((noipa))
void vrem_int8_t (int8_t * __restrict dst, int8_t * __re
OK.
This is also the approach I took locally to fix a Fortran ICE
but forgot to send/push it.
Regards
Robin
Hi Lehua,
> V3 Change: Back to the original method.
Was there an original method even before the first patch?
Anyway, I prefer this v3 over the others even though the large
pattern is not exactly pretty :)
What about the VLS changes? Are they necessary for the patterns/tests?
I mean they are re
So when diamond bb support was added to minmax_replacement in
r13-1950-g9bb19e143cfe,
the code was not expecting the alt_middle_bb not to exist if it was empty (for
threeway_p).
So when factor_out_conditional_conversion was used to factor out conversions,
it turns out
the assumption for alt_midd
From: Haochen Jiang
gcc/ChangeLog:
* config/i386/i386-builtin.def (BDESC): Add
OPTION_MASK_ISA2_EVEX512.
---
gcc/config/i386/i386-builtin.def | 156 +++
1 file changed, 78 insertions(+), 78 deletions(-)
diff --git a/gcc/config/i386/i386-builtin.def b
From: Haochen Jiang
gcc/ChangeLog:
* config/i386/i386-expand.cc (ix86_broadcast_from_constant):
Disable zmm broadcast for !TARGET_EVEX512.
* config/i386/i386-options.cc (ix86_option_override_internal):
Do not use PVW_512 when no-evex512.
(ix86_simd_clone_a
From: Haochen Jiang
gcc/ChangeLog:
* config/i386/i386-builtins.cc
(ix86_vectorize_builtin_gather): Disable 512 bit gather
when !TARGET_EVEX512.
* config/i386/i386-expand.cc (ix86_valid_mask_cmp_mode):
Add TARGET_EVEX512.
(ix86_expand_int_sse_cmp):
From: Haochen Jiang
gcc/ChangeLog:
* config/i386/avx512bwintrin.h: Add evex512 target for 512 bit
intrins.
---
gcc/config/i386/avx512bwintrin.h | 291 ---
1 file changed, 153 insertions(+), 138 deletions(-)
diff --git a/gcc/config/i386/avx512bwintrin
From: Haochen Jiang
gcc/Changelog:
* config/i386/i386-expand.cc (ix86_expand_vector_init_duplicate):
Make sure there is EVEX512 enabled.
(ix86_expand_vecop_qihi2): Refuse V32QI->V32HI when no EVEX512.
* config/i386/i386.cc (ix86_hard_regno_mode_ok): Disable 64 bit
From: Haochen Jiang
gcc/ChangeLog:
* config/i386/i386-builtin.def (BDESC): Add
OPTION_MASK_ISA2_EVEX512.
---
gcc/config/i386/i386-builtin.def | 188 +++
1 file changed, 94 insertions(+), 94 deletions(-)
diff --git a/gcc/config/i386/i386-builtin.def b
From: Haochen Jiang
gcc/ChangeLog:
* config.gcc: Add avx512bitalgvlintrin.h.
* config/i386/avx5124fmapsintrin.h: Add evex512 target for 512 bit
intrins.
* config/i386/avx5124vnniwintrin.h: Ditto.
* config/i386/avx512bf16intrin.h: Ditto.
* config/i3
From: Haochen Jiang
gcc/ChangeLog:
* config/i386/i386-builtin.def (BDESC): Add
OPTION_MASK_ISA2_EVEX512.
* config/i386/i386-builtins.cc
(ix86_init_mmx_sse_builtins): Ditto.
---
gcc/config/i386/i386-builtin.def | 648 +++
gcc/config/i38
From: Haochen Jiang
gcc/ChangeLog:
* config/i386/sse.md (V48H_AVX512VL): Add TARGET_EVEX512.
(VFH): Ditto.
(VF2H): Ditto.
(VFH_AVX512VL): Ditto.
(VHFBF): Ditto.
(VHF_AVX512VL): Ditto.
(VI2H_AVX512VL): Ditto.
(VI2F_256_512): Ditto.
From: Haochen Jiang
gcc/ChangeLog:
* config/i386/avx512dqintrin.h: Add evex512 target for 512 bit
intrins.
---
gcc/config/i386/avx512dqintrin.h | 1840 +++---
1 file changed, 926 insertions(+), 914 deletions(-)
diff --git a/gcc/config/i386/avx512dqintrin
From: Haochen Jiang
gcc/ChangeLog:
* config/i386/i386.opt: Allow -mno-evex512.
gcc/testsuite/ChangeLog:
* gcc.target/i386/noevex512-1.c: New test.
* gcc.target/i386/noevex512-2.c: Ditto.
* gcc.target/i386/noevex512-3.c: Ditto.
---
gcc/config/i386/i386.opt
From: Haochen Jiang
gcc/ChangeLog:
* config/i386/i386-expand.cc (ix86_expand_sse2_mulvxdi3):
Add TARGET_EVEX512 for 512 bit usage.
* config/i386/i386.cc (standard_sse_constant_opcode): Ditto.
* config/i386/sse.md (VF1_VF2_AVX512DQ): Ditto.
(VF1_128_256VL):
From: Haochen Jiang
gcc/ChangeLog:
* config/i386/i386-builtin.def (BDESC): Add
OPTION_MASK_ISA2_EVEX512.
---
gcc/config/i386/i386-builtin.def | 226 +++
1 file changed, 113 insertions(+), 113 deletions(-)
diff --git a/gcc/config/i386/i386-builtin.def
From: Haochen Jiang
gcc/ChangeLog:
* config/i386/sse.md (VI1_AVX512VL): Add TARGET_EVEX512.
(VI8_FVL): Ditto.
(VI1_AVX512F): Ditto.
(VI1_AVX512VNNI): Ditto.
(VI1_AVX512VL_F): Ditto.
(VI12_VI48F_AVX512VL): Ditto.
(*avx512f_permvar_truncv32hi
From: Haochen Jiang
gcc/ChangeLog:
* config/i386/i386-builtin.def (BDESC): Add
OPTION_MASK_ISA2_EVEX512.
---
gcc/config/i386/i386-builtin.def | 94
1 file changed, 47 insertions(+), 47 deletions(-)
diff --git a/gcc/config/i386/i386-builtin.def b
Hi all,
After previous discussion, instead of supporting option -mavx10.1, we
will first introduct option -m[no-]evex512, which will enable/disable
512 bit register and 64 bit mask register.
It will not change the current option behavior since if AVX512F is
enabled with no evex512 option specifie
From: Haochen Jiang
gcc/ChangeLog:
* common/config/i386/i386-common.cc
(OPTION_MASK_ISA2_EVEX512_SET): New.
(OPTION_MASK_ISA2_EVEX512_UNSET): Ditto.
(ix86_handle_option): Handle EVEX512.
* config/i386/i386-c.cc (ix86_target_macros_internal): Ditto.
This patch adjusts the comments of the
emit_vlmax_insn/emit_vlmax_insn_lra/emit_nonvlmax_insn functions.
The purpose of the adjustment is to make it clear that vlmax here is not
VLMAX as defined inside the RVV ISA. This is because this function is used
by RVV mode (e.g. RVVM1SImode) in addition to
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