For LoongArch, the toplevel library build is always aliased to
one of the multilib variants. This patch installs it with the
actual MULTISUBDIR (instead of ".") so that the headers can be
reached by the compiler.
This patch is an update of
https://gcc.gnu.org/pipermail/gcc-patches/2023-September/
On Wed, Sep 6, 2023 at 9:43 PM Vladimir Makarov wrote:
>
>
> On 9/1/23 05:07, Hongyu Wang wrote:
> > Uros Bizjak via Gcc-patches 于2023年8月31日周四 18:16写道：
> >> On Thu, Aug 31, 2023 at 10:20 AM Hongyu Wang wrote:
> >>> From: Kong Lingling
> >>>
> >>> Current reload infrastructure does not support s
Committed, thanks Kito.
Pan
-Original Message-
From: Gcc-patches On Behalf
Of Kito Cheng via Gcc-patches
Sent: Thursday, September 7, 2023 11:39 AM
To: Juzhe-Zhong
Cc: GCC Patches ; Kito Cheng
Subject: Re: [PATCH] RISC-V: Remove incorrect earliest vsetvl post
optimization[PR111313]
LGTM
Juzhe-Zhong 於 2023年9月7日 週四 11:36 寫道：
> This patch removes the incorrect earliest poset vsetvl optimization,
> such bug was found in vect-double-reduc-5.c which is runtime(execution
> fail) and also in PR111313.
>
> For VLMAX intrinsics, we always emit a bogus patter which is vlmax_avl
> (se
This patch removes the incorrect earliest poset vsetvl optimization,
such bug was found in vect-double-reduc-5.c which is runtime(execution fail)
and also in PR111313.
For VLMAX intrinsics, we always emit a bogus patter which is vlmax_avl (see
vector.md) to
occupy a scalar register which is used
Hi,
As discussed in PR111303:
For pattern "(X + C) / N": "div (plus@3 @0 INTEGER_CST@1) INTEGER_CST@2)",
Even if "X" has value-range and "X + C" does not overflow, "@3" may still
be undefined. Like below example:
_3 = _2 + -5;
if (0 != 0)
goto ; [34.00%]
else
goto ; [66.00%]
;; succ:
Hi Robin,
Yes, you're right, this should not be necessary. This is more of a
test for the execution environment than the compiler. I think Juzhe
removed it already in his patch that enables the vector test suite.
In the future we would use the checks that Joern added, not sure if
they are alre
On Wed, Sep 06, 2023 at 06:38:25PM +0800, Xi Ruoyao wrote:
> On Wed, 2023-09-06 at 18:06 +0800, Yang Yujie wrote:
> > When multilib is enabled, the c++ header directory of the default multilib
> > variant needs to be linked to the toplevel since g++ does not search the
> > toplevel in this case.
>
在 2023-09-06三的 18:56 +0800，Xi Ruoyao写道：
> On Wed, 2023-09-06 at 18:45 +0800, Xiaolong Chen wrote:
> > + *((int*)& __m128_op0[3]) = 0x004200a0;
> > + *((int*)& __m128_op0[2]) = 0x;
> > + *((int*)& __m128_op0[1]) = 0x004200a0;
> > + *((int*)& __m128_op0[0]) = 0x0021;
>
> These are al
This patch rebases the change of "[PATCH] RISC-V: Optimize the MASK opt
generation" and add the new explanation in the options.texi.
gcc/ChangeLog:
* config/riscv/riscv-opts.h (MASK_ZICSR):
(MASK_ZIFENCEI): Delete;
(MASK_ZIHINTNTL):Ditto;
(MASK_ZIHINTPAUSE):
From: Tsukasa OI
This commit replaces the type of the builtin used in the testsuite.
Even without this commit, it won't cause any test failures but changed so
that no confusion occurs.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/zbc32.c: Make signed type to unsigned.
* gcc.targ
From: Tsukasa OI
For bit manipulation operations, inputs and the manipulated output are
better to be unsigned like other target-independent builtins like
__builtin_bswap32 and __builtin_popcount.
Although this is not completely compatible as before (as the type changes),
most code will run norma
Hello,
Many RISC-V builtins operate in signed integer types but in many cases,
they are better to be unsigned.
There are a few reasons to do that:
1. Being more natural
For bit manipulation operations, the direct input and the result should
have an unsigned type.
e.g. __builtin_bswa
在 2023/9/6 下午6:58, Xi Ruoyao 写道:
Forgot to mention: I've bootstrapped and regtested this patch on
loongarch64-linux-gnu (with PR110939 patch applied to unbreak the
bootstrapping). Ok for trunk?
LGTM!
Thanks!
On Wed, 2023-09-06 at 18:46 +0800, Xi Ruoyao wrote:
If mask is a constant with
Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}.
Ready push to trunk.
gcc/ChangeLog:
* config/i386/sse.md
(_vpermt2var3): New define_insn.
(VHFBF_AVX512VL): New mode iterator.
(VI2HFBF_AVX512VL): New mode iterator.
---
gcc/config/i386/sse.md | 32
在 2023/9/6 下午7:10, Xi Ruoyao 写道:
On Wed, 2023-09-06 at 18:43 +0800, Xiaolong Chen wrote:
gcc/testsuite/ChangeLog:
* gcc.target/loongarch/strict-align.c: New test.
A question: is there really a CPU model with LSX/LASX but without
unaligned access support? If not I think we'd just re
Thanks reminder, I should rebase again.
--
Feng Wang
>Hi,
>
>I will need to notify you that x_riscv_xventana_subext,
>MASK_XVENTANACONDOPS and TARGET_XVENTANACONDOPS are added (I think you
>want to rewrite those definitions like the rest). Also, be careful not
>to remove TARGET_ZICOND_
Hi,
I will need to notify you that x_riscv_xventana_subext,
MASK_XVENTANACONDOPS and TARGET_XVENTANACONDOPS are added (I think you
want to rewrite those definitions like the rest). Also, be careful not
to remove TARGET_ZICOND_LIKE.
Thanks,
Tsukasa
On 2023/09/06 11:02, Feng Wang wrote:
> This pa
On 2023/09/07 2:50, Edwin Lu wrote:
> This patch creates a new "zicond" type and updates all zicond instructions
> with that type.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv.md: Add "zicond" type
> * config/riscv/zicond.md: Update types
>
> Signed-off-by: Edwin Lu
> ---
> gcc/conf
> Date: Thu, 7 Sep 2023 00:11:04 +0100
> From: Jonathan Wakely via Gcc-patches
> On Thu, 7 Sept 2023 at 00:10, Jonathan Wakely wrote:
> > I don't think there's a bug. $is_hosted is true for
> > --enable-hosted-libstdcxx which is on by default.
>
> And IIRC __STDC_HOSTED__ is defined unless you
csr is kind of confusing, I would suggest something like `pushpop` and
`mvpair`.
Edwin Lu 於 2023年9月7日 週四 01:51 寫道：
> This patch adds types to the untyped zc instructions. Creates a new
> type "csr" for these instructions for now.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv.md: Add "csr"
LGTM
Edwin Lu 於 2023年9月7日 週四 01:51 寫道：
> This patch adds types to vector instructions that were added after or were
> missed by the original patch
> https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628594.html
>
> gcc/ChangeLog:
>
> * config/riscv/autovec-opt.md: Update types
>
LGTM
Edwin Lu 於 2023年9月7日 週四 01:52 寫道：
> This patch adds types to riscv instructions that were added or were
> missed by the original patch
> https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628996.html
>
> gcc/ChangeLog:
>
> * config/riscv/riscv.md: Update types
>
> Signed-off-by:
LGTM
Edwin Lu 於 2023年9月7日 週四 01:53 寫道：
> This patch creates a new "zicond" type and updates all zicond instructions
> with that type.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv.md: Add "zicond" type
> * config/riscv/zicond.md: Update types
>
> Signed-off-by: Edwin Lu
> ---
> g
On Thu, 7 Sept 2023 at 00:10, Jonathan Wakely wrote:
>
> On Thu, 7 Sept 2023 at 00:09, Hans-Peter Nilsson wrote:
> >
> > > From: Jonathan Wakely
> > > Date: Wed, 6 Sep 2023 23:30:08 +0100
> >
> > > On Mon, 4 Sept 2023 at 17:49, Jonathan Wakely
> > > wrote:
> > > >
> > > > On Mon, 4 Sept 2023 a
On Thu, 7 Sept 2023 at 00:09, Hans-Peter Nilsson wrote:
>
> > From: Jonathan Wakely
> > Date: Wed, 6 Sep 2023 23:30:08 +0100
>
> > On Mon, 4 Sept 2023 at 17:49, Jonathan Wakely wrote:
> > >
> > > On Mon, 4 Sept 2023 at 17:47, Hans-Peter Nilsson via Libstdc++
> > > wrote:
> > > >
> > > > > Date:
> From: Jonathan Wakely
> Date: Wed, 6 Sep 2023 23:30:08 +0100
> On Mon, 4 Sept 2023 at 17:49, Jonathan Wakely wrote:
> >
> > On Mon, 4 Sept 2023 at 17:47, Hans-Peter Nilsson via Libstdc++
> > wrote:
> > >
> > > > Date: Fri, 1 Sep 2023 12:16:40 +0100
> > > > Reply-To: Jonathan Wakely
> > > >
>
This patch to godump.cc adds support for BITINT_TYPE. Bootstrapped
and ran godump and Go tests on x86_64-pc-linux-gnu. Committed to
mainline.
Ian
gcc/
PR go/111310
* godump.cc (go_format_type): Handle BITINT_TYPE.
gcc/testsuite/
PR go/111310
* gcc
On Mon, 4 Sept 2023 at 17:49, Jonathan Wakely wrote:
>
> On Mon, 4 Sept 2023 at 17:47, Hans-Peter Nilsson via Libstdc++
> wrote:
> >
> > > Date: Fri, 1 Sep 2023 12:16:40 +0100
> > > Reply-To: Jonathan Wakely
> > >
> > > On Wed, 23 Aug 2023 at 17:03, Jonathan Wakely via Libstdc++
> > > wrote:
>
Tested x86_64-linux and x86_64-elf. Pushed to trunk.
-- >8 --
libstdc++-v3/ChangeLog:
* acinclude.m4 (GLIBCXX_ENABLE_BACKTRACE): Disable by default
for freestanding.
* configure: Regenerate.
---
libstdc++-v3/acinclude.m4 | 2 +-
libstdc++-v3/configure| 2 +-
2 files
On Mon, 28 Aug 2023, Jason Merrill wrote:
> On 8/24/23 09:31, Patrick Palka wrote:
> > On Wed, 23 Aug 2023, Jason Merrill wrote:
> >
> > > On 8/21/23 21:51, Patrick Palka wrote:
> > > > Bootstrapped and regtested on x86_64-pc-linux-gnu, does this look like
> > > > a reasonable approach? I didn't
Bootstrapped and regtested on x86_64-pc-linux-gnu, does this look OK for
trunk? This cache apparently has a 98% hit rate for TYPE_HAS_CONVERSION
types on some test files.
-- >8 --
gcc/cp/ChangeLog:
* config-lang.in (gtfiles): Add search.cc.
* search.cc (lookup_conversions_cache)
On Mon, 28 Aug 2023, Jason Merrill wrote:
> On 8/24/23 09:31, Patrick Palka wrote:
> > On Wed, 23 Aug 2023, Jason Merrill wrote:
> >
> > > On 8/21/23 21:51, Patrick Palka wrote:
> > > > Bootstrapped and regtested on x86_64-pc-linux-gnu, does this look like
> > > > a reasonable approach? I did
On Sat, 26 Aug 2023, Martin Uecker via Gcc-patches wrote:
> -static int
> +static bool
> comp_target_types (location_t location, tree ttl, tree ttr)
The comment above this function should be updated to refer to returning
true, not to returning 1. And other comments on common_pointer_type and
Robin Dapp writes:
> Hi Richard,
>
> I did some testing with the attached v2 that does not restrict to UNARY
> anymore. As feared ;) there is some more fallout that I'm detailing below.
>
> On Power there is one guality fail (pr43051-1.c) that I would take
> the liberty of ignoring for now.
>
> O
On Wed, 2023-09-06 at 21:16 +0200, priour...@gmail.com wrote:
[...snip...]
> Signed-off-by: benjamin priour
> Co-authored-by: david malcolm
Please also add:
Signed-off-by: David Malcolm
[...snip...]
>
> +static bool
> +compatible_epath_p (const exploded_path *lhs_path,
> +
On Wed, 2023-09-06 at 15:50 +0200, Benjamin Priour wrote:
> Hi David,
> Thanks for the review.
>
>
>
> On Tue, Sep 5, 2023 at 1:53 PM David Malcolm
> wrote:
>
> > On Mon, 2023-09-04 at 20:00 +0200, priour...@gmail.com wrote:
> >
> >
> [...snip...]
>
>
> > All of these "new" tests (apart fr
On 9/1/23 05:07, Hongyu Wang wrote:
Uros Bizjak via Gcc-patches 于2023年8月31日周四 18:16写道：
On Thu, Aug 31, 2023 at 10:20 AM Hongyu Wang wrote:
From: Kong Lingling
Current reload infrastructure does not support selective base_reg_class
for backend insn. Add insn argument to base_reg_class for
From: benjamin priour
Hi,
Second version of this patch after David's suggestions.
Thanks David for pointing out how I could implement it using sedges.
I hadn't thought of them being independent of the exploded path taken,
and unique for a conditional block's outcome. I had mistaken them with
eed
On Wed, 06 Sep 2023 09:47:05 PDT (-0700), jeffreya...@gmail.com wrote:
On 9/6/23 10:22, Palmer Dabbelt wrote:
On Wed, 06 Sep 2023 09:07:33 PDT (-0700), christoph.muell...@vrull.eu
wrote:
From: Christoph Müllner
This patch implements the expansion of the strlen builtin for RV32/RV64
for xlen
This libgo patch changes the go tool to permit the AR environment
variable to include options. This mirrors the way it already handles
the CC environment variable.
This ports https://go.dev/cl/526275 to the gofrontend repo.
This is needed for gccgo testing because the top-level GCC Makefile
now
This patch turns on the assert which ensures every instruction has type
that is not TYPE_UNKNOWN.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_sched_variable_issue): Remove assert
Signed-off-by: Edwin Lu
---
gcc/config/riscv/riscv.cc | 2 --
1 file changed, 2 deletions(-)
diff --git
This patch creates a new "zicond" type and updates all zicond instructions
with that type.
gcc/ChangeLog:
* config/riscv/riscv.md: Add "zicond" type
* config/riscv/zicond.md: Update types
Signed-off-by: Edwin Lu
---
gcc/config/riscv/riscv.md | 5 +++--
gcc/config/riscv/zicond.
This patch adds types to riscv instructions that were added or were
missed by the original patch
https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628996.html
gcc/ChangeLog:
* config/riscv/riscv.md: Update types
Signed-off-by: Edwin Lu
---
gcc/config/riscv/riscv.md | 3 +++
1 file
This patch adds types to the untyped zc instructions. Creates a new
type "csr" for these instructions for now.
gcc/ChangeLog:
* config/riscv/riscv.md: Add "csr" type
* config/riscv/zc.md: Update types
Signed-off-by: Edwin Lu
---
gcc/config/riscv/riscv.md | 3 +-
gcc/config/ri
This patch adds types to vector instructions that were added after or were
missed by the original patch
https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628594.html
gcc/ChangeLog:
* config/riscv/autovec-opt.md: Update types
* config/riscv/autovec.md: likewise
Signed-off-by:
This series adds types to the remaining untyped instructions.
Related Discussion:
https://inbox.sourceware.org/gcc-patches/12fb5088-3f28-0a69-de1e-f387371a5...@gmail.com/
Also enables assert which checks to make sure every instruction has a type
All patches were tested with rv32/rv64 linux/newli
On 9/6/23 10:22, Palmer Dabbelt wrote:
On Wed, 06 Sep 2023 09:07:33 PDT (-0700), christoph.muell...@vrull.eu
wrote:
From: Christoph Müllner
This patch implements the expansion of the strlen builtin for RV32/RV64
for xlen-aligned aligned strings if Zbb or XTheadBb instructions are
available
On Wed, 06 Sep 2023 09:07:33 PDT (-0700), christoph.muell...@vrull.eu wrote:
From: Christoph Müllner
This patch implements the expansion of the strlen builtin for RV32/RV64
for xlen-aligned aligned strings if Zbb or XTheadBb instructions are available.
The inserted sequences are:
rv32gc_zbb (R
On Tue, Sep 05, 2023 at 10:40:26PM +, Joseph Myers wrote:
> Additional tests I think should be added (for things I expect should
> already work):
>
> * Tests for BITINT_MAXWIDTH in . Test that it's defined for
> C2x, but not defined for C11/C17 (the latter independent of whether the
> targ
From: Christoph Müllner
This patch implements the expansion of the strlen builtin for RV32/RV64
for xlen-aligned aligned strings if Zbb or XTheadBb instructions are available.
The inserted sequences are:
rv32gc_zbb (RV64 is similar):
add a3,a0,4
li a4,-1
.L1: lw a5,0(a
From: Christoph Müllner
This patch implements expansions for the cmpstrsi and cmpstrnsi
builtins for RV32/RV64 for xlen-aligned strings if Zbb or XTheadBb
instructions are available. The expansion basically emits a comparison
sequence which compares XLEN bits per step if possible.
This allows t
From: Christoph Müllner
This series introduces strlen/strcmp/strncmp inline expansion for Zbb/XTheadBb.
In the last months, glibc as well as the Linux kernel merged changes for
optimized string processing for RISC-V. The instruction, which enables
optimized string routines is Zbb's orc.b (or T-H
Hi!
Thanks for the patch reviews (and to Richi and Uros as well) and everyone
who participated in discussions.
Here is the updated version of the C _BitInt support [PR102989] patch
I've committed to trunk in addition to the rest of the series (except the
_BitInt a ? ~b : b match.pd fix patch, whi
Hi,
ping**2 on the revised patch, for Richard or another global reviewer. So far
all review feedback is that it’s a step forward, and it’s been widely used for
both aarch64-darwin and x86_64-darwin distributions for almost three years now.
OK to commit?
FX
> Le 5 août 2023 à 16:20, FX Couder
This patch fix incorrect mode tieable between DI and V2SI which cause ICE
in RA.
PR target/111296
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_modes_tieable_p): Fix incorrect mode
tieable for RVV modes.
gcc/testsuite/ChangeLog:
* g++.target/riscv/rvv/base/pr111296.C:
On 9/6/23 16:12, David Malcolm wrote:
On Wed, 2023-09-06 at 15:53 +0200, Arthur Cohen wrote:
From: David Malcolm
I guess I can review this patch :)
Needs a ChangeLog entry, so here's one:
gcc/ChangeLog
* diagnostic-core.h (error_meta): New decl.
* diagnostic.cc (error_meta):
On Wed, 2023-09-06 at 15:53 +0200, Arthur Cohen wrote:
> From: David Malcolm
This is probably something for the gcc-rust maintainers to review
(rather than me self-reviewing with my "diagnostics maintainer" hat
on).
Doesn't have a ChangeLog entry, FWIW.
Doesn't have a signed-off-by, so here's on
On Wed, 2023-09-06 at 15:53 +0200, Arthur Cohen wrote:
> From: David Malcolm
I guess I can review this patch :)
Needs a ChangeLog entry, so here's one:
gcc/ChangeLog
* diagnostic-core.h (error_meta): New decl.
* diagnostic.cc (error_meta): New.
Also, needs a signed-off-by, so h
On 9/5/23 23:47, Tsukasa OI wrote:
From: Tsukasa OI
'XVentanaCondOps' is a vendor extension from Ventana Micro Systems
containing two instructions for conditional move and will be supported on
their Veyron V1 CPU.
And most notably (for historical reasons), 'XVentanaCondOps' and the
standard
On 9/6/23 03:47, Juzhe-Zhong wrote:
This patch fix incorrect mode tieable between DI and V2SI which cause ICE
in RA.
PR target/111296
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_modes_tieable_p): Fix bug.
gcc/testsuite/ChangeLog:
* g++.target/riscv/rvv/base/pr111
Committed, thanks Robin.
Pan
-Original Message-
From: Gcc-patches On Behalf
Of Robin Dapp via Gcc-patches
Sent: Wednesday, September 6, 2023 9:39 PM
To: Juzhe-Zhong ; gcc-patches@gcc.gnu.org
Cc: kito.ch...@sifive.com; kito.ch...@gmail.com
Subject: Re: [PATCH] RISC-V: Remove unreasonable
Committed, thanks Robin.
Pan
-Original Message-
From: Gcc-patches On Behalf
Of Robin Dapp via Gcc-patches
Sent: Wednesday, September 6, 2023 9:38 PM
To: Juzhe-Zhong ; gcc-patches@gcc.gnu.org
Cc: kito.ch...@sifive.com; kito.ch...@gmail.com
Subject: Re: [PATCH] RISC-V: Fix VSETVL PASS AVL
Hi.
I'll do another test to make sure this is enough since I tested with a
few more finalize functions.
Thanks a lot for finding this!
On Wed, 2023-09-06 at 09:40 -0400, David Malcolm via Jit wrote:
> As part of Antoyo's work on supporting LTO in rustc_codegen_gcc, he
> noticed an ICE inside libgc
Hi David,
Thanks for the review.
On Tue, Sep 5, 2023 at 1:53 PM David Malcolm wrote:
> On Mon, 2023-09-04 at 20:00 +0200, priour...@gmail.com wrote:
>
>
[...snip...]
> All of these "new" tests (apart from the "-noexcept" ones) look like
> they're meant to be existing tests that were moved, b
From: David Malcolm
---
gcc/rust/rust-diagnostics.cc | 11 +++
gcc/rust/rust-diagnostics.h | 18 ++
gcc/rust/rust-gcc-diagnostics.cc | 33 +++
gcc/rust/typecheck/rust-casts.cc | 2 +-
.../rust/compile/bad_a
From: David Malcolm
---
gcc/diagnostic-core.h | 3 +++
gcc/diagnostic.cc | 15 +++
2 files changed, 18 insertions(+)
diff --git a/gcc/diagnostic-core.h b/gcc/diagnostic-core.h
index 7334c79e8e6..c9e27fd2e6e 100644
--- a/gcc/diagnostic-core.h
+++ b/gcc/diagnostic-core.h
@@ -92,6
This short patchset from David Malcolm enables errors to contain extra
metadata - this is particularly useful for the Rust frontend, which will
rely on that implementation to emit standard Rust error codes [1].
This series of patches is necessary for much of our more recent
additions to the fronte
Successfully bootstrapped & regrtested on x86_64-pc-linux-gnu.
Pushed to trunk as r14-3741-gf2d7a4001a3388.
gcc/analyzer/ChangeLog:
PR analyzer/105899
* kf.cc (class kf_strstr): New.
(kf_strstr::impl_call_post): New.
(register_known_functions): Register it.
gcc/tes
Successfully bootstrapped & regrtested on x86_64-pc-linux-gnu.
Pushed to trunk as r14-3740-gb51cde34d4e750.
gcc/analyzer/ChangeLog:
PR analyzer/105899
* kf.cc (class kf_strncpy): New.
(kf_strncpy::impl_call_post): New.
(register_known_functions): Register it.
I noticed that region_model's fill_region/zero_fill_region member
functions weren't checking that the write to the region was valid.
Fixed thusly.
Successfully bootstrapped & regrtested on x86_64-pc-linux-gnu.
Pushed to trunk as r14-3739-gb923978a6ec447.
gcc/analyzer/ChangeLog:
* kf.cc (
As part of Antoyo's work on supporting LTO in rustc_codegen_gcc, he
noticed an ICE inside libgccjit when compiling certain rust files.
Debugging libgccjit showed that outdated information from a previous
in-memory compile was referring to ad-hoc locations in the previous
compile's line_table.
The
LGTM.
Regards
Robin
OK.
Regards
Robin
Hi Lehua,
> May I ask if the compiler options "-march=rv64gcv_zvfh -mabi=lp64d"
> should be removed? Because we don't specify -march and -mabi when we
> run testcase (so but why we need to specify the -march and -mabi in
> this target check?), we run it with the default values. Assuming that
> t
Hi Juzhe,
general remark upfront: Please add function-level comments for all
functions. This makes reading and reviewing much easier. I had to sweep
back and forth quite a bit.
> +
> +static int
> +get_last_live_range (const vec &live_ranges, tree var)
> +{
> + unsigned int ix;
> + var_live_
Committed, thanks Juzhe and sorry for my silly mistake.
Pan
From: juzhe.zhong
Sent: Wednesday, September 6, 2023 8:53 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; Li, Pan2 ; Wang, Yanzhang
; kito.ch...@gmail.com
Subject: Re: [PATCH v1] RISC-V: Fix incorrect folder for VRGATHERI16 test case
lg
From: Pan Li
Put the test file to the incorrect folder, this patch would like to
fix it.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/intrisinc-vrgatherei16.c: Moved to...
* gcc.target/riscv/rvv/base/intrisinc-vrgatherei16.c: ...here.
Signed-off-by: Pan Li
---
.../gcc.targ
This patch covers signed and unsigned subtractions. The generated code
would be something along these lines:
signed:
sub.f r0, r1, r2
b.v @label
unsigned:
sub.f r0, r1, r2
b.c @label
gcc/ChangeLog:
* config/arc/arc.md (subsi3_v): New insn.
(subvsi4): New exp
This patch covers signed and unsigned additions. The generated code
would be something along these lines:
signed:
add.f r0, r1, r2
b.v @label
unsigned:
add.f r0, r1, r2
b.c @label
gcc/ChangeLog:
* config/arc/arc-modes.def: Add CC_V mode.
* config/arc/predica
Fix bugzilla: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111295
PR target/111295
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc (insert_vsetvl):
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/pr111295.c: New test.
---
gcc/config/riscv/riscv-vsetvl.cc
Yang Yujie writes:
> gcc/ChangeLog:
>
> * config.gcc: remove non-POSIX syntax "<<<".
OK. Thanks for the quick fix.
Richard.
> ---
> gcc/config.gcc | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/gcc/config.gcc b/gcc/config.gcc
> index b2fe7c7ceef..6d4c8becd28 10
Previously, I add TARGET_64BIT condtion to block VLS modes with size = 64bit
in RV32 system
E.g. V8QI
Since I realized such modes may cause inferior codegen for some situations in
RV32 system.
However, this is really quite ugly and it cause ICE for some cases in RV32:
FAIL: gcc.target/riscv/r
Hello folks,
Here's v3 of the top part of the security policy. Hopefully this
addresses all concerns raised so far.
Thanks,
Sid
What is a GCC security bug?
===
A security bug is one that threatens the security of a system or
network, or might compromise the
Hi Richard,
I did some testing with the attached v2 that does not restrict to UNARY
anymore. As feared ;) there is some more fallout that I'm detailing below.
On Power there is one guality fail (pr43051-1.c) that I would take
the liberty of ignoring for now.
On x86 there are four fails:
- con
Committed, thanks Kito.
--
Best,
Lehua
On Wed, 2023-09-06 at 18:43 +0800, Xiaolong Chen wrote:
> gcc/testsuite/ChangeLog:
>
> * gcc.target/loongarch/strict-align.c: New test.
A question: is there really a CPU model with LSX/LASX but without
unaligned access support? If not I think we'd just reject -mstrict-
align -mlsx.
Curr
Yang Yujie writes:
> gcc/ChangeLog:
>
> * config.gcc: remove non-POSIX syntax "<<<".
> ---
Thanks, I was just about to report this.
> gcc/config.gcc | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/gcc/config.gcc b/gcc/config.gcc
> index b2fe7c7ceef..6d4c8becd28
Forgot to mention: I've bootstrapped and regtested this patch on
loongarch64-linux-gnu (with PR110939 patch applied to unbreak the
bootstrapping). Ok for trunk?
On Wed, 2023-09-06 at 18:46 +0800, Xi Ruoyao wrote:
> If mask is a constant with value ((1 << N) - 1) << M we can perform this
> optimi
On Wed, 2023-09-06 at 18:45 +0800, Xiaolong Chen wrote:
> + *((int*)& __m128_op0[3]) = 0x004200a0;
> + *((int*)& __m128_op0[2]) = 0x;
> + *((int*)& __m128_op0[1]) = 0x004200a0;
> + *((int*)& __m128_op0[0]) = 0x0021;
These are aliasing rule violation and they will suddenly blow up w
If mask is a constant with value ((1 << N) - 1) << M we can perform this
optimization.
gcc/ChangeLog:
PR target/111252
* config/loongarch/loongarch-protos.h
(loongarch_pre_reload_split): Declare new function.
(loongarch_use_bstrins_for_ior_with_mask): Likewise.
gcc/testsuite/ChangeLog:
* gcc.target/loongarch/vector/lsx/lsx-builtin.c: New test.
---
.../loongarch/vector/lsx/lsx-builtin.c| 1461 +
1 file changed, 1461 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-builtin.c
diff --git a/
gcc/testsuite/ChangeLog:
* gcc.target/loongarch/vector/loongarch-vector.exp: New test.
* gcc.target/loongarch/vector/simd_correctness_check.h: New test.
---
.../loongarch/vector/loongarch-vector.exp | 42 +++
.../loongarch/vector/simd_correctness_check.h | 39 +
gcc/testsuite/ChangeLog:
* gcc.target/loongarch/strict-align.c: New test.
---
gcc/testsuite/gcc.target/loongarch/strict-align.c | 13 +
1 file changed, 13 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/loongarch/strict-align.c
diff --git a/gcc/testsuite/gcc.target
In order to better test the function of the vector instruction, the 128 and 256
bit test cases are further split according to the function of the instruction.
Xiaolong Chen (4):
LoongArch: Add tests of -mstrict-align option.
LoongArch: Add testsuite framework for Loongson SX/ASX.
LoongArch:
On Wed, 2023-09-06 at 18:06 +0800, Yang Yujie wrote:
> When multilib is enabled, the c++ header directory of the default multilib
> variant needs to be linked to the toplevel since g++ does not search the
> toplevel in this case.
>
> libstdc++-v3/ChangeLog:
>
> * configure.host: Register
On Tue, Sep 5, 2023 at 2:29 AM Takayuki 'January June' Suwa
wrote:
>
> This patch optimizes the boolean evaluation for equality to 0 in SImode
> using the MINU (Minimum Value Unsigned) machine instruction available
> when TARGET_MINMAX is configured, for example, (x != 0) to MINU(x, 1)
> and (x ==
On Tue, Sep 5, 2023 at 9:24 PM Takayuki 'January June' Suwa
wrote:
> On 2023/09/06 8:01, Max Filippov wrote:
> > On Tue, Sep 5, 2023 at 2:29 AM Takayuki 'January June' Suwa
> > wrote:
> >> ;; after (prereq. TARGET_MINMAX)
> >> test0:
> >> movi.n a9, 1
> >> minua2, a2,
reminder: ready for commit?
- Javier
On Wed 23. Aug 2023 at 15:02, Javier Martinez <
javier.martinez.bugzi...@gmail.com> wrote:
> On Tue, Aug 22, 2023 at 7:50 PM Jason Merrill wrote:
> > You still need an update to doc/extend.texi for this additional use of
> > the attribute. Sorry I didn't th
Committed as "obvious" to master.
--Philipp.
On Wed, 6 Sept 2023 at 12:04, Christoph Muellner <
christoph.muell...@vrull.eu> wrote:
> From: Christoph Müllner
>
> The test was introduced recently and tests a RV64-only feature.
> However, when testing an RV32 compiler, the test gets executed as we
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