LGTM

Edwin Lu <e...@rivosinc.com> 於 2023年9月7日 週四 01:53 寫道:

> This patch creates a new "zicond" type and updates all zicond instructions
> with that type.
>
> gcc/ChangeLog:
>
>         * config/riscv/riscv.md: Add "zicond" type
>         * config/riscv/zicond.md: Update types
>
> Signed-off-by: Edwin Lu <e...@rivosinc.com>
> ---
>  gcc/config/riscv/riscv.md  | 5 +++--
>  gcc/config/riscv/zicond.md | 8 ++++----
>  2 files changed, 7 insertions(+), 6 deletions(-)
>
> diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
> index 6684ad89cff..c329f55db43 100644
> --- a/gcc/config/riscv/riscv.md
> +++ b/gcc/config/riscv/riscv.md
> @@ -313,6 +313,7 @@ (define_attr "ext_enabled" "no,yes"
>  ;; cbo    cache block instructions
>  ;; crypto cryptography instructions
>  ;; csr    code size reduction instructions
> +;; zicond    zicond instructions
>  ;; Classification of RVV instructions which will be added to each RVV .md
> pattern and used by scheduler.
>  ;; rdvlenb     vector byte length vlenb csrr read
>  ;; rdvl        vector length vl csrr read
> @@ -422,8 +423,8 @@ (define_attr "type"
>     mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul,
>     fmadd,fdiv,fcmp,fcvt,fsqrt,multi,auipc,sfb_alu,nop,trap,ghost,bitmanip,
>     rotate,clmul,min,max,minu,maxu,clz,ctz,cpop,
> -   atomic,condmove,cbo,crypto,csr,rdvlenb,rdvl,wrvxrm,wrfrm,rdfrm,vsetvl,
> -   vlde,vste,vldm,vstm,vlds,vsts,
> +   atomic,condmove,cbo,crypto,csr,zicond,rdvlenb,rdvl,wrvxrm,wrfrm,rdfrm,
> +   vsetvl, vlde,vste,vldm,vstm,vlds,vsts,
>     vldux,vldox,vstux,vstox,vldff,vldr,vstr,
>
> vlsegde,vssegte,vlsegds,vssegts,vlsegdux,vlsegdox,vssegtux,vssegtox,vlsegdff,
>     vialu,viwalu,vext,vicalu,vshift,vnshift,vicmp,viminmax,
> diff --git a/gcc/config/riscv/zicond.md b/gcc/config/riscv/zicond.md
> index 1721e1011ea..0269bd14399 100644
> --- a/gcc/config/riscv/zicond.md
> +++ b/gcc/config/riscv/zicond.md
> @@ -30,7 +30,7 @@ (define_insn "*czero.<eqz>.<GPR:mode><X:mode>"
>                            (const_int 0)))]
>    "TARGET_ZICOND"
>    "czero.<eqz>\t%0,%2,%1"
> -)
> +[(set_attr "type" "zicond")])
>
>  (define_insn "*czero.<nez>.<GPR:mode><X:mode>"
>    [(set (match_operand:GPR 0 "register_operand"                     "=r")
> @@ -40,7 +40,7 @@ (define_insn "*czero.<nez>.<GPR:mode><X:mode>"
>                            (match_operand:GPR 2 "register_operand"
>  "r")))]
>    "TARGET_ZICOND"
>    "czero.<nez>\t%0,%2,%1"
> -)
> +[(set_attr "type" "zicond")])
>
>  ;; Special optimization under eq/ne in primitive semantics
>  (define_insn "*czero.eqz.<GPR:mode><X:mode>.opt1"
> @@ -51,7 +51,7 @@ (define_insn "*czero.eqz.<GPR:mode><X:mode>.opt1"
>                            (match_operand:GPR 3 "register_operand" "r")))]
>    "TARGET_ZICOND && rtx_equal_p (operands[1], operands[2])"
>    "czero.eqz\t%0,%3,%1"
> -)
> +[(set_attr "type" "zicond")])
>
>  (define_insn "*czero.nez.<GPR:mode><X:mode>.opt2"
>    [(set (match_operand:GPR 0 "register_operand"                   "=r")
> @@ -61,7 +61,7 @@ (define_insn "*czero.nez.<GPR:mode><X:mode>.opt2"
>                            (match_operand:GPR 3 "register_operand" "1")))]
>    "TARGET_ZICOND && rtx_equal_p (operands[1], operands[3])"
>    "czero.eqz\t%0,%2,%1"
> -)
> +[(set_attr "type" "zicond")])
>
>  ;; Combine creates this form in some cases (particularly the coremark
>  ;; CRC loop.
> --
> 2.34.1
>
>

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